PIC18F96J65T-I/PT Microchip Technology, PIC18F96J65T-I/PT Datasheet - Page 62

• Manufacturer Part Number: PIC18F96J65T-I/PT
• Description: 96KB Flash, 12KB RAM, 10BASE-T Ethernet 100 TQFP 12x12x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F96J65T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 96KB (48K x 16)
• Program Memory Type: FLASH
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver, Ethernet, EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183033, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100AC164323 - MODULE SKT FOR 100TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F97J60 FAMILY
4.7
Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset
state” depending on the type of Reset that occurred.
Most registers are not affected by a WDT wake-up
since this is viewed as the resumption of normal
operation. Status bits from the RCON register (CM, RI,
TABLE 4-1:
DS39762E-page 62
Power-on Reset
RESET Instruction
Brown-out Reset
Configuration Mismatch Reset
MCLR during power-managed
Run modes
MCLR during power-managed
Idle modes and Sleep mode
MCLR during full-power
execution
Stack Full Reset (STVREN = 1)
Stack Underflow Reset
(STVREN = 1)
Stack Underflow Error (not an
actual Reset, STVREN = 0)
WDT time-out during full power
or power-managed Run modes
WDT time-out during
power-managed Idle or Sleep
modes
Interrupt exit from
power-managed modes
Legend: u = unchanged
Note 1:
Reset State of Registers
Condition
When the wake-up is due to an interrupt, and the GIEH or GIEL bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
Counter
Program
PC + 2
PC + 2
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
(1)
CM
1
u
1
0
u
u
u
u
u
u
u
u
u
RI
1
0
1
u
u
u
u
u
u
u
u
u
u
RCON Register
TO, PD, POR and BOR) are set or cleared differently in
different Reset situations, as indicated in Table 4-1.
These bits are used in software to determine the nature
of the Reset.
Table 4-2 describes the Reset states for all of the
Special Function Registers. These are categorized by
Power-on and Brown-out Resets, Master Clear and
WDT Resets and WDT wake-ups.
TO
1
u
1
u
1
1
u
u
u
u
0
0
u
PD
1
u
1
u
u
0
u
u
u
u
u
0
0
POR
0
u
u
u
u
u
u
u
u
u
u
u
u
© 2009 Microchip Technology Inc.
BOR
0
u
0
u
u
u
u
u
u
u
u
u
u
STKFUL STKUNF
STKPTR Register
0
u
u
u
u
u
u
1
u
u
u
u
u
0
u
u
u
u
u
u
u
1
1
u
u
u