PIC18LF13K22-E/P Microchip Technology, PIC18LF13K22-E/P Datasheet - Page 135

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PIC18LF13K22-E/P

Manufacturer Part Number
PIC18LF13K22-E/P
Description
8KB Flash, 256bytes RAM, 256bytes EEPROM, 16MIPS, NanoWatt XLP 20 PDIP .300in TU
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr

Specifications of PIC18LF13K22-E/P

Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
14.0
14.1
The Master Synchronous Serial Port (MSSP) module is
a serial interface, useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers, dis-
play drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I
The I
hardware:
• Master mode
• Multi-Master mode
• Slave mode
 2010 Microchip Technology Inc.
- Full Master mode
- Slave mode (with general address call)
2
C interface supports the following modes in
MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
Master SSP (MSSP) Module
Overview
2
C™)
Preliminary
PIC18F1XK22/LF1XK22
14.2
The SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. All four
modes
communication, typically three pins are used:
• Serial Data Out – SDO
• Serial Data In – SDI
• Serial Clock – SCK
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select – SS
Figure 14-1 shows the block diagram of the MSSP
module when operating in SPI mode.
FIGURE 14-1:
SCK/SCL
SDI/SDA
SDO
SS
SPI Mode
of
SPI
Read
are
SS Control
TRIS bit
Select
Edge
MSSP BLOCK DIAGRAM
(SPI MODE)
Select
bit 0
Edge
Enable
supported.
SSPBUF Reg
SSPSR Reg
Clock Select
SSPM<3:0>
4
DS41365D-page 135
2
To
(
Prescaler
4, 16, 64
TMR2 Output
Write
Clock
Shift
accomplish
Data Bus
Internal
2
T
OSC
)

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