PIC18LF13K50T-I/SS Microchip Technology, PIC18LF13K50T-I/SS Datasheet - Page 393

8 KB Flash, 512 RAM, 15 I/O, 10-bit ADC, USB 2.0, NanoWatt XLP 20 SSOP .209in T/

PIC18LF13K50T-I/SS

Manufacturer Part Number
PIC18LF13K50T-I/SS
Description
8 KB Flash, 512 RAM, 15 I/O, 10-bit ADC, USB 2.0, NanoWatt XLP 20 SSOP .209in T/
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr

Specifications of PIC18LF13K50T-I/SS

Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
14
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SSOP
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART, I2C, MSSP, SPI, USB
Maximum Clock Frequency
32 KHz
Number Of Programmable I/os
18
Number Of Timers
4
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM164127, DV164126
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
TABLE 27-15: SPI MODE REQUIREMENTS
FIGURE 27-19:
 2010 Microchip Technology Inc.
Param
SP70* T
SP71* T
SP72* T
SP73* T
SP74* T
SP75* T
SP76* T
SP77* T
SP78* T
SP79* T
SP80* T
SP81* T
SP82* T
SP83* T
No.
SCL
SDA
Note: Refer to
*
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
T
T
T
T
T
T
SS
SS
SC
SC
SC
SC
SS
SC
SC
SC
SC
SS
SC
SC
DI
DI
DO
DO
DO
DO
Symbol
These parameters are characterized but not tested.
only and are not tested.
V2
V2
L2
L2
H
L
H2
L2
H2
R
F
H2
L2
L2
H2
L2
R
F
V2
V2
SC
SC
SC
SC
DO
SP90
DI
DO
SS
DI
DO
DO
SS
SC
SC
L
L,
Figure 27-2
H,
L
H,
L
H
V
V
H,
Z
V,
H,
L
SS to SCK or SCK input
SCK input high time (Slave mode)
SCK input low time (Slave mode)
Setup time of SDI data input to SCK edge
Hold time of SDI data input to SCK edge
SDO data output rise time
SDO data output fall time
SS to SDO output high-impedance
SCK output rise time
(Master mode)
SCK output fall time (Master mode)
SDO data output valid after
SCK edge
SDO data output setup to SCK edge
SDO data output valid after SS edge
SS after SCK edge
I
2
Condition
C™ BUS START/STOP BITS TIMING
Start
for load conditions.
SP91
Characteristic
Preliminary
3.0-5.5V
1.8-5.5V
3.0-5.5V
1.8-5.5V
3.0-5.5V
1.8-5.5V
1.5T
T
T
CY
CY
PIC18F/LF1XK50
Min
T
100
100
Tcy
CY
10
CY
+ 20
+ 20
+ 40
SP92
Typ†
10
25
10
10
25
10
Condition
Max Units Conditions
Stop
145
25
50
25
50
25
50
25
50
50
DS41350E-page 393
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SP93

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