PIC18LF26K80T-I/MM Microchip Technology, PIC18LF26K80T-I/MM Datasheet - Page 467
PIC18LF26K80T-I/MM
Manufacturer Part Number
PIC18LF26K80T-I/MM
Description
ECAN, 64KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 28 QFN-S 6x6mm T/R
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F25K80-ISO.pdf
(628 pages)
Specifications of PIC18LF26K80T-I/MM
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
ECAN, I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Processor Series
PIC18LF26K80
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3648 B
Interface Type
I2C, SPI
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
24
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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REGISTER 28-5:
2011 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6-4
bit 3
bit 2
bit 1
bit 0
Note 1:
MCLRE
R/P-1
Implemented only on the 64-pin devices (PIC18F6XK80). Maintain as ‘ 0 ’ on 28-pin, 40-pin and 44-pin
devices.
MCLRE: MCLR Pin Enable bit
1 = MCLR pin is enabled; RE3 input pin is disabled
0 = RE3 input pin is enabled; MCLR is disabled
Unimplemented: Read as ‘ 0 ’
MSSPMSK: MSSP V3 7-Bit Address Masking Mode Enable bit
1 = 7-Bit Address Masking mode is enabled
0 = 5-Bit Address Masking mode is enabled
T3CKMX: Timer3 Clock Input MUX bit
1 = Timer3 gets its clock input from the RG2/T3CKI pin on 64-pin packages
0 = Timer3 gets its clock input from the RB5/T3CKI pin on 64-pin packages
T0CKMX: Timer0 Clock Input MUX bit
1 = Timer0 gets its clock input from the RB5/T0CKI pin on 64-pin packages
0 = Timer0 gets its clock input from the RG4/T0CKI pin on 64-pin packages
CANMX: ECAN MUX bit
1 = CANTX and CANRX pins are located on RB2 and RB3, respectively
0 = CANTX and CANRX pins are located on RC6 and RC7, respectively (28-pin and 40/44-pin
packages) or on RE4 and RE5, respectively (64-pin package)
U-0
—
CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h)
P = Programmable bit
W = Writable bit
‘1’ = Bit is set
U-0
—
U-0
Preliminary
—
(1)
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
MSSPMSK
PIC18F66K80 FAMILY
R/P-1
T3CKMX
R/P-1
(1)
x = Bit is unknown
T0CKMX
R/P-1
DS39977C-page 467
(1)
CANMX
R/P-1
bit 0
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