PIC18LF26K80T-I/MM Microchip Technology, PIC18LF26K80T-I/MM Datasheet - Page 481
![ECAN, 64KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 28 QFN-S 6x6mm T/R](/photos/16/12/161267/qfn-28_sml.jpg)
PIC18LF26K80T-I/MM
Manufacturer Part Number
PIC18LF26K80T-I/MM
Description
ECAN, 64KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 28 QFN-S 6x6mm T/R
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F25K80-ISO.pdf
(628 pages)
Specifications of PIC18LF26K80T-I/MM
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
ECAN, I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Processor Series
PIC18LF26K80
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3648 B
Interface Type
I2C, SPI
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
24
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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28.5
The Fail-Safe Clock Monitor (FSCM) allows the
microcontroller to continue operation in the event of an
external oscillator failure by automatically switching the
device clock to the internal oscillator block. The FSCM
function is enabled by setting the FCMEN Configuration
bit.
When FSCM is enabled, the LF-INTOSC oscillator runs
at all times to monitor clocks to peripherals and provide
a backup clock in the event of a clock failure. Clock
monitoring (shown in
creating a sample clock signal, which is the output from
the LF-INTOSC divided by 64. This allows ample time
between FSCM sample clocks for a peripheral clock
edge to occur. The peripheral device clock and the
sample clock are presented as inputs to the Clock
Monitor (CM) latch. The CM is set on the falling edge of
the device clock source, but cleared on the rising edge
of the sample clock.
FIGURE 28-4:
Clock failure is tested for on the falling edge of the
sample clock. If a sample clock falling edge occurs
while CM is still set, a clock failure has been detected
(Figure
• The FSCM generates an oscillator fail interrupt by
• The device clock source switches to the internal
• The WDT is reset
During switchover, the postscaler frequency from the
internal oscillator block may not be sufficiently stable for
timing-sensitive applications. In these cases, it may be
desirable to select another clock configuration and enter
an alternate power-managed mode. This can be done to
attempt a partial recovery or execute a controlled shut-
down. See
and
Using Two-Speed Start-up”
2011 Microchip Technology Inc.
Peripheral
setting bit, OSCFIF (PIR2<7>)
oscillator block (OSCCON is not updated to show
the current clock source – this is the fail-safe
condition)
INTOSC
Source
(32 s)
Clock
Section 28.4.1 “Special Considerations for
28-5). This causes the following:
Fail-Safe Clock Monitor
Section 4.1.4 “Multiple Sleep Commands”
(2.048 ms)
488 Hz
÷ 64
Figure
FSCM BLOCK DIAGRAM
(edge-triggered)
Clock Monitor
Latch (CM)
28-4) is accomplished by
for more details.
C
S
Q
Q
Detected
Failure
Clock
Preliminary
PIC18F66K80 FAMILY
To use a higher clock speed on wake-up, the INTOSC
or postscaler clock sources can be selected to provide
a higher clock speed by setting bits, IRCF<2:0>,
immediately after Reset. For wake-ups from Sleep, the
INTOSC or postscaler clock sources can be selected
by setting the IRCF<2:0> bits prior to entering Sleep
mode.
The FSCM will detect only failures of the primary or
secondary clock sources. If the internal oscillator block
fails, no failure would be detected nor would any action
be possible.
28.5.1
Both the FSCM and the WDT are clocked by the
INTOSC oscillator. Since the WDT operates with a
separate divider and counter, disabling the WDT has
no effect on the operation of the INTOSC oscillator
when the FSCM is enabled.
As already noted, the clock source is switched to the
INTOSC clock when a clock failure is detected.
Depending on the frequency selected by the
IRCF<2:0> bits, this may mean a substantial change in
the speed of code execution. If the WDT is enabled
with a small prescale value, a decrease in clock speed
allows a WDT time-out to occur and a subsequent
device Reset. For this reason, Fail-Safe Clock events
also reset the WDT and postscaler, allowing it to start
timing from when execution speed was changed and
decreasing the likelihood of an erroneous time-out.
28.5.2
The Fail-Safe condition is terminated by either a device
Reset or by entering a power-managed mode. On
Reset, the controller starts the primary clock source
specified in Configuration Register 1H (with any
required start-up delays that are required for the
oscillator mode, such as the OST or PLL timer). The
INTOSC multiplexer provides the device clock until the
primary clock source becomes ready (similar to a Two-
Speed Start-up). The clock source is then switched to
the primary clock (indicated by the OSTS bit in the
OSCCON register becoming set). The Fail-Safe Clock
Monitor then resumes monitoring the peripheral clock.
The primary clock source may never become ready
during start-up. In this case, operation is clocked by the
INTOSC multiplexer. The OSCCON register will remain
in its Reset state until a power-managed mode is
entered.
FSCM AND THE WATCHDOG TIMER
EXITING FAIL-SAFE OPERATION
DS39977C-page 481
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