PIC18LF4458T-I/ML Microchip Technology, PIC18LF4458T-I/ML Datasheet - Page 29
![24KB Flash, 2KB RAM, 256 Bytes EEPROM, 35 I/O, USB, 12bit ADC 44 QFN 8x8x0.9mm T](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC18LF4458T-I/ML
Manufacturer Part Number
PIC18LF4458T-I/ML
Description
24KB Flash, 2KB RAM, 256 Bytes EEPROM, 35 I/O, USB, 12bit ADC 44 QFN 8x8x0.9mm T
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2221-ISO.pdf
(46 pages)
2.PIC18F2458-ISO.pdf
(46 pages)
3.PIC18F2458-ISO.pdf
(6 pages)
4.PIC18F2458-ISO.pdf
(6 pages)
5.PIC18F2458-ISO.pdf
(6 pages)
Specifications of PIC18LF4458T-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
24KB (12K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 13x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
2.6
Figure 2-4 shows the operation of the A/D Converter
after the GO/DONE bit has been set and the
ACQT2:ACQT0 bits are cleared. A conversion is
started after the following instruction to allow entry into
Sleep mode before the conversion begins.
Figure 2-5 shows the operation of the A/D Converter
after the GO/DONE bit has been set and the
ACQT2:ACQT0 bits are set to ‘010’, and selecting a
4 T
Clearing the GO/DONE bit during a conversion will abort
the current conversion. The A/D Result register pair will
NOT be updated with the partially completed A/D
conversion sample. This means the ADRESH:ADRESL
registers will continue to contain the value of the last
completed conversion (or the last value written to the
ADRESH:ADRESL registers).
FIGURE 2-4:
FIGURE 2-5:
© 2009 Microchip Technology Inc.
(Holding capacitor continues
acquiring input)
Set GO/DONE bit
T
AD
Set GO/DONE bit
CY
Holding capacitor is disconnected from analog input (typically 100 ns)
1
acquisition time before the conversion starts.
– T
T
ACQT
A/D Conversions
Acquisition
AD
Automatic
2
Time
T
AD
Cycles
1 T
3
Conversion starts
b11
AD
A/D CONVERSION T
2 T
A/D CONVERSION T
4
AD
b10
1
3 T
Conversion starts
(Holding capacitor is disconnected)
AD
b11
b9
2
4 T
b10
AD
On the following cycle:
ADRESH:ADRESL are loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
3
b8
5 T
On the following cycle:
ADRESH:ADRESL are loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
PIC18F2458/2553/4458/4553
AD
AD
b9
AD
4
b7
6 T
CYCLES (ACQT<2:0> = 000, T
CYCLES (ACQT<2:0> = 010, T
b8
5
AD
b6
7 T
b7
T
6
AD
AD
b5
8
Cycles
After the A/D conversion is completed or aborted, a
2 T
be started. After this wait, acquisition on the selected
channel is automatically started.
2.7
The discharge phase is used to initialize the value of
the holding capacitor. The array is discharged before
every sample. This feature helps to optimize the unity
gain amplifier, as the circuit always needs to charge the
capacitor array, rather than charge/discharge based on
previous measure values.
b6
7
Note:
T
CY
AD
b4
wait is required before the next acquisition can
9 T
b5
8
Discharge
AD
b3
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
Code should wait at least 2 μs after
enabling the A/D before beginning an
acquisition and conversion cycle.
10
b4
9
T
AD
b2
11
10
b3
ACQ
T
ACQ
AD
b1
11
b2
12
= 0)
= 4 T
T
AD
b0
12
b1
13
AD
)
DS39887C-page 29
T
Discharge
(typically 200 ns)
b0
13
AD
1
T
Discharge
(typically
200 ns)
AD
1