PIC24F04KA200T-I/ST Microchip Technology, PIC24F04KA200T-I/ST Datasheet - Page 122
PIC24F04KA200T-I/ST
Manufacturer Part Number
PIC24F04KA200T-I/ST
Description
PIC24F Core, 4KB Flash, 512B RAM, 3V, Deep Sleep, 10-bit 500ksps ADC, CTMU, UART
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr
Datasheets
1.PIC24F04KA201-ISS.pdf
(8 pages)
2.PIC24F04KA201-ISS.pdf
(48 pages)
3.PIC24F04KA201-ISS.pdf
(224 pages)
4.PIC24F04KA201-ISS.pdf
(26 pages)
Specifications of PIC24F04KA200T-I/ST
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
4KB (1.375K x 24)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
14-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24F04KA200T-I/ST
Manufacturer:
MICROCHIP
Quantity:
12 000
- PIC24F04KA201-ISS PDF datasheet
- PIC24F04KA201-ISS PDF datasheet #2
- PIC24F04KA201-ISS PDF datasheet #3
- PIC24F04KA201-ISS PDF datasheet #4
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- Download datasheet (4Mb)
PIC24F04KA201 FAMILY
REGISTER 15-1:
DS39937B-page 120
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12-11
bit 10-8
bit 7
bit 6
bit 5
bit 4-2
R-0,HSC
SRMPT
SPIEN
R/W-0
HS = Hardware Settable bit
SPIEN: SPI1 Enable bit
1 = Enables module and configures SCK1, SDO1, SDI1 and SS1 as serial port pins
0 = Disables module
Unimplemented: Read as ‘0’
SPISIDL: Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
Unimplemented: Read as ‘0’
SPIBEC<2:0>: SPI1 Buffer Element Count bits (valid in Enhanced Buffer mode)
Master mode:
Number of SPI transfers pending.
Slave mode:
Number of SPI transfers unread.
SRMPT: Shift Register (SPI1SR) Empty bit (valid in Enhanced Buffer mode)
1 = SPI1 Shift register is empty and ready to send or receive
0 = SPI1 Shift register is not empty
SPIROV: Receive Overflow Flag bit
1 = A new byte/word is completely received and discarded. The user software has not read the previous
0 = No overflow has occurred
SRXMPT: Receive FIFO Empty bit (valid in Enhanced Buffer mode)
1 = Receive FIFO is empty
0 = Receive FIFO is not empty
SISEL<2:0>: SPI1 Buffer Interrupt Mode bits (valid in Enhanced Buffer mode)
111 = Interrupt when SPI1 transmit buffer is full (SPITBF bit is set)
110 = Interrupt when last bit is shifted into SPI1SR; as a result, the TX FIFO is empty
101 = Interrupt when the last bit is shifted out of SPI1SR; now the transmit is complete
100 = Interrupt when one data byte is shifted into the SPI1SR; as a result, the TX FIFO has one open spot
011 = Interrupt when SPI1 receive buffer is full (SPIRBF bit set)
010 = Interrupt when SPI1 receive buffer is 3/4 or more full
001 = Interrupt when data is available in receive buffer (SRMPT bit is set)
000 = Interrupt when the last data in the receive buffer is read; as a result, the buffer is empty
R/C-0, HS
SPIROV
data in the SPI1BUF register.
U-0
—
SPI1STAT: SPI1 STATUS AND CONTROL REGISTER
(SRXMPT bit is set)
W = Writable bit
‘1’ = Bit is set
R/W-0, HSC
SRXMPT
SPISIDL
R/W-0
HSC = Hardware Settable/Clearable bit
SISEL2
R/W-0
U-0
—
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
SISEL1
R/W-0
U-0
—
R-0, HSC
SPIBEC2
SISEL0
R/W-0
© 2009 Microchip Technology Inc.
C = Clearable bit
x = Bit is unknown
R-0, HSC
SPIBEC1
R-0, HSC
SPITBF
R-0, HSC
SPIBEC0
R-0, HSC
SPIRBF
bit 8
bit 0
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