PIC24F04KA201T-I/SO Microchip Technology, PIC24F04KA201T-I/SO Datasheet - Page 87
PIC24F04KA201T-I/SO
Manufacturer Part Number
PIC24F04KA201T-I/SO
Description
PIC24F Core, 4KB Flash, 512B RAM, 3V, Deep Sleep, 10-bit 500ksps ADC, CTMU, UART
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr
Datasheets
1.PIC24F04KA201-ISS.pdf
(8 pages)
2.PIC24F04KA201-ISS.pdf
(48 pages)
3.PIC24F04KA201-ISS.pdf
(224 pages)
4.PIC24F04KA201-ISS.pdf
(26 pages)
Specifications of PIC24F04KA201T-I/SO
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
4KB (1.375K x 24)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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REGISTER 8-2:
© 2009 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14-12
bit 11
bit 10-8
bit 7-0
Note 1:
R/W-0
ROI
U-0
—
This bit is automatically cleared when the ROI bit is set and an interrupt occurs.
ROI: Recover on Interrupt bit
1 = Interrupts clear the DOZEN bit and reset the CPU and peripheral clock ratio to 1:1
0 = Interrupts have no effect on the DOZEN bit
DOZE<2:0>: CPU and Peripheral Clock Ratio Select bits
111 = 1:128
110 = 1:64
101 = 1:32
100 = 1:16
011 = 1:8
010 = 1:4
001 = 1:2
000 = 1:1
DOZEN: DOZE Enable bit
1 = DOZE<2:0> bits specify the CPU and peripheral clock ratio
0 = CPU and peripheral clock ratio set to 1:1
RCDIV<2:0>: FRC Postscaler Select bits
When OSCCON (COSC<2:0>) = 111:
111 = 31.25 kHz (divide by 256)
110 = 125 kHz (divide by 64)
101 = 250 kHz (divide by 32)
100 = 500 kHz (divide by 16)
011 = 1 MHz (divide by 8)
010 = 2 MHz (divide by 4)
001 = 4 MHz (divide by 2) (default)
000 = 8 MHz (divide by 1)
When OSCCON (COSC<2:0>) = 110:
111 = 1.95 kHz (divide by 256)
110 = 7.81 kHz (divide by 64)
101 = 15.62 kHz (divide by 32)
100 = 31.25 kHz (divide by 16)
011 = 62.5 kHz (divide by 8)
010 = 125 kHz (divide by 4)
001 = 250 kHz (divide by 2) (default)
000 = 500 kHz (divide by 1)
Unimplemented: Read as ‘0’
DOZE2
R/W-0
U-0
—
CLKDIV: CLOCK DIVIDER REGISTER
W = Writable bit
‘1’ = Bit is set
DOZE1
R/W-1
U-0
—
(1)
DOZE0
R/W-1
U-0
—
Preliminary
PIC24F04KA201 FAMILY
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
DOZEN
R/W-0
U-0
—
(1)
RCDIV2
R/W-0
U-0
—
x = Bit is unknown
RCDIV1
R/W-0
U-0
—
DS39937B-page 85
RCDIV0
R/W-1
U-0
—
bit 8
bit 0
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