PIC24F04KA201T-I/SS Microchip Technology, PIC24F04KA201T-I/SS Datasheet - Page 10
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PIC24F04KA201T-I/SS
Manufacturer Part Number
PIC24F04KA201T-I/SS
Description
PIC24F Core, 4KB Flash, 512B RAM, 3V, Deep Sleep, 10-bit 500ksps ADC, CTMU, UART
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr
Datasheets
1.PIC24F04KA201-ISS.pdf
(8 pages)
2.PIC24F04KA201-ISS.pdf
(48 pages)
3.PIC24F04KA201-ISS.pdf
(224 pages)
4.PIC24F04KA201-ISS.pdf
(26 pages)
Specifications of PIC24F04KA201T-I/SS
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
4KB (1.375K x 24)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
PIC24FXXKA2XX
3.6
The procedure for writing code memory is the same as
writing the Configuration registers. The difference is
that the 32 instruction words are programmed one at a
time. To facilitate this operation, working registers,
W0:W5, are used as temporary holding registers for the
data to be programmed.
memory writing flow.
Table 3-5
including the serial pattern with the ICSP command
code, which must be transmitted, LSB first, using the
PGCx and PGDx pins (see
In Step 1 of
Step 2, the NVMCON register is initialized for
programming a full row of code memory. In Step 3, the
24-bit starting destination address for programming is
loaded into the TBLPAG register and W7 register. The
upper byte of the starting destination address is stored
in TBLPAG and the lower 16 bits of the destination
address are stored in W7.
To minimize the programming time, a packed
instruction format is used (see
In Step 4 of
are stored in working registers, W0:W5, using the MOV
instruction; the Read Pointer, W6, is initialized.
Figure 3-7
the packed instruction word data. In Step 5, eight
TBLWT instructions are used to copy the data from
W0:W5 to the write latches of the code memory. Since
code memory is programmed 32 instruction words at a
time, Steps 3 to 5 are repeated eight times to load all
the write latches (see Step 6).
TABLE 3-5:
DS39991A-page 10
Step 1: Exit the Reset vector.
Step 2: Set the NVMCON to program 32 instruction words.
Step 3: Initialize the Write Pointer (W7) for TBLWT instruction.
Command
(Binary)
0000
0000
0000
0000
0000
0000
0000
0000
Writing Code Memory
provides the ICSP programming details,
illustrates the contents of W0:W5 holding
Table
Table
SERIAL INSTRUCTION EXECUTION FOR WRITING CODE MEMORY
3-5, the Reset vector is exited. In
3-5, four packed instruction words
000000
040200
000000
24004A
883B0A
200xx0
880190
2xxxx7
(Hex)
Data
Figure 3-8
Figure
Figure
3-2).
NOP
GOTO
NOP
MOV
MOV
MOV
MOV
MOV
illustrates the code
3-7).
0x200
#0x4004, W10
W10, NVMCON
#<DestinationAddress23:16>, W0
W0, TBLPAG
#<DestinationAddress15:0>, W7
After the write latches are loaded, initiate programming
by writing to the NVMCON register in Steps 7 and 8. In
Step 9, the internal PC is reset to 200h. This is a
precautionary measure to prevent the PC from
incrementing to unimplemented memory when large
devices are being programmed. Finally, in Step 10,
repeat Steps 3 through 9 until all of the code memory is
programmed.
FIGURE 3-7:
W0
W1
W2
W3
W4
W5
Description
15
MSB1
MSB3
PACKED INSTRUCTION
WORDS IN W0:W5
2010 Microchip Technology Inc.
LSW0
LSW1
LSW2
LSW3
8 7
MSB0
MSB2
0