PIC24F04KA201T-I/SS Microchip Technology, PIC24F04KA201T-I/SS Datasheet - Page 13
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PIC24F04KA201T-I/SS
Manufacturer Part Number
PIC24F04KA201T-I/SS
Description
PIC24F Core, 4KB Flash, 512B RAM, 3V, Deep Sleep, 10-bit 500ksps ADC, CTMU, UART
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr
Datasheets
1.PIC24F04KA201-ISS.pdf
(8 pages)
2.PIC24F04KA201-ISS.pdf
(48 pages)
3.PIC24F04KA201-ISS.pdf
(224 pages)
4.PIC24F04KA201-ISS.pdf
(26 pages)
Specifications of PIC24F04KA201T-I/SS
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
4KB (1.375K x 24)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
3.7
The procedure for writing the Configuration registers is
the same as for writing code memory. The only differ-
ence is that only one word is programmed in each
operation. When writing Configuration registers, one
word is programmed during each operation. Only work-
ing register, W0, is used as a temporary holding register
for the data to be programmed.
Table 3-6
Configuration registers.
Table 3-6
programming the Configuration registers, including the
serial pattern with the ICSP command code, which
must be transmitted, LSB first, using the PGCx and
PGDx pins (see
Reset vector is exited. In Step 2, the NVMCON register
is initialized for programming code memory. In Step 3,
the 24-bit starting destination address for programming
is loaded into the TBLPAG register and W7 register.
2010 Microchip Technology Inc.
Note:
Note:
Writing Configuration Registers
provides the ICSP programming details for
provides
The TBLPAG register is hard-coded to
0xF8 (the upper byte address of all
locations of the Configuration registers).
The TBLPAG register must be loaded with
F8h.
Figure
the
3-2). In Step 1 of
default
values
Table
of
3-7, the
the
TABLE 3-6:
FGS
FOSCSEL
FOSC
FWDT
FPOR
FICD
FDS
Note 1:
Configuration
Registers
(1)
PIC24FXXKA2XX
The Configuration register, FICD, is a
reserved location and should be
programmed with the default value given
above.
DEFAULT VALUES FOR
CONFIGURATION REGISTER
SERIAL INSTRUCTION
Value
FFh
DFh
FBh
C3h
FFh
03h
87h
DS39991A-page 13