PIC24FJ32GA102-E/SS Microchip Technology, PIC24FJ32GA102-E/SS Datasheet - Page 69

16-bit, 16 MIPS, 32KB Flash, 8KB RAM, Nanowatt XLP 28 SSOP .209in TUBE

PIC24FJ32GA102-E/SS

Manufacturer Part Number
PIC24FJ32GA102-E/SS
Description
16-bit, 16 MIPS, 32KB Flash, 8KB RAM, Nanowatt XLP 28 SSOP .209in TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr
Datasheet

Specifications of PIC24FJ32GA102-E/SS

Processor Series
PIC24
Core
PIC24F
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
32 KB
Data Ram Size
8192 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
21
Number Of Timers
5
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
SSOP-28
Development Tools By Supplier
MPLAB Integrated Development Environment
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 125 C
Supply Current (max)
300 mA
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
21
Eeprom Size
-
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Lead Free Status / Rohs Status
 Details
REGISTER 7-1:
REGISTER 7-2:
 2010 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-5
Note 1:
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 3
Note 1:
IPL2
R/W-0
U-0
U-0
U-0
2:
3:
2:
(2,3)
See Register 3-1 for the description of the remaining bit(s) that are not dedicated to interrupt control
functions.
The IPL bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU interrupt priority level.
The value in parentheses indicates the interrupt priority level if IPL3 = 1.
The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1.
See Register 3-2 for the description of the remaining bit(s) that are not dedicated to interrupt control
functions.
The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level.
IPL<2:0>: CPU Interrupt Priority Level Status bits
111 = CPU interrupt priority level is 7 (15). User interrupts are disabled.
110 = CPU interrupt priority level is 6 (14)
101 = CPU interrupt priority level is 5 (13)
100 = CPU interrupt priority level is 4 (12)
011 = CPU interrupt priority level is 3 (11)
010 = CPU interrupt priority level is 2 (10)
001 = CPU interrupt priority level is 1 (9)
000 = CPU interrupt priority level is 0 (8)
IPL3: CPU Interrupt Priority Level Status bit
1 = CPU interrupt priority level is greater than 7
0 = CPU interrupt priority level is 7 or less
IPL1
R/W-0
U-0
U-0
U-0
SR: ALU STATUS REGISTER (IN CPU)
CORCON: CPU CONTROL REGISTER
(2,3)
W = Writable bit
‘1’ = Bit is set
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
IPL0
R/W-0
U-0
U-0
U-0
(2,3)
RA
PIC24FJ64GA104 FAMILY
U-0
R-0
U-0
U-0
(1)
U = Unimplemented bit, read as ‘0’
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
‘0’ = Bit is cleared
(2)
IPL3
R/W-0
R/C-0
U-0
N
U-0
(1)
(2,3)
(2)
PSV
R/W-0
R/W-0
OV
U-0
U-0
(1)
(1)
x = Bit is unknown
x = Bit is unknown
R/W-0
U-0
Z
U-0
U-0
(1)
DS39951C-page 69
R/W-0
DC
C
R-0
U-0
U-0
(1)
(1)
bit 8
bit 0
bit 8
bit 0

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