PIC24FJ64GA108-E/PT Microchip Technology, PIC24FJ64GA108-E/PT Datasheet - Page 172
![16-bit, 16 MIPS, 64KB Flash, 16Kb RAM, 84 I/O, NanoWatt 80 TQFP 12x12x1mm TRAY](/photos/16/13/161322/tqfp64_sml.jpg)
PIC24FJ64GA108-E/PT
Manufacturer Part Number
PIC24FJ64GA108-E/PT
Description
16-bit, 16 MIPS, 64KB Flash, 16Kb RAM, 84 I/O, NanoWatt 80 TQFP 12x12x1mm TRAY
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Datasheet
1.PIC24FJ128GA106-IPT.pdf
(330 pages)
Specifications of PIC24FJ64GA108-E/PT
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
64KB (22K x 24)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
*
Processor Series
PIC24FJ256GA110
Core
PIC
Data Bus Width
16 bit
Data Ram Size
16 KB
Interface Type
UART, I2C, SPI
Maximum Clock Frequency
8 MHz
Number Of Timers
5
Operating Supply Voltage
3.6 V
Maximum Operating Temperature
- 40 C to + 85 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24FJ64GA108-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- Current page: 172 of 330
- Download datasheet (3Mb)
PIC24FJ256GA110 FAMILY
REGISTER 14-1:
DS39905E-page 172
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-14
bit 13
bit 12-10
bit 9-8
bit 7
bit 6-5
bit 4
bit 3
bit 2-0
Note 1:
ENFLT0
R/W-0
U-0
—
2:
The OCx output must also be configured to an available RPn pin. For more information, see
“Peripheral Pin
OCFA pin controls OC1-OC4 channels; OCFB pin controls the OC5-OC9 channels. OCxR and OCxRS are
double-buffered only in PWM modes.
Unimplemented: Read as ‘0’
OCSIDL: Stop Output Compare x in Idle Mode Control bit
1 = Output Compare x halts in CPU Idle mode
0 = Output Compare x continues to operate in CPU Idle mode
OCTSEL<2:0>: Output Compare x Timer Select bits
111 = Peripheral Clock (F
110 = Reserved
101 = Reserved
100 = Timer1
011 = Timer5
010 = Timer4
001 = Timer3
000 = Timer2
Unimplemented: Read as ‘0’
ENFLT0: Fault 0 Input Enable bit
1 = Fault 0 input is enabled
0 = Fault 0 input is disabled
Unimplemented: Read as ‘0’
OCFLT0: PWM Fault Condition Status bit
1 = PWM Fault condition has occurred (cleared in HW only)
0 = No PWM Fault condition has occurred (this bit is only used when OCM<2:0> = 111)
TRIGMODE: Trigger Status Mode Select bit
1 = TRIGSTAT (OCxCON2<6>) is cleared when OCxRS = OCxTMR or in software
0 = TRIGSTAT is only cleared by software
OCM<2:0>: Output Compare x Mode Select bits
111 = Center-Aligned PWM mode on OCx
110 = Edge-Aligned PWM mode on OCx
101 = Double Compare Continuous Pulse mode: initialize OCx pin low, toggle OCx state continuously
100 = Double Compare Single-Shot mode: initialize OCx pin low, toggle OCx state on matches of OCxR
011 = Single Compare Continuous Pulse mode: compare events continuously toggle OCx pin
010 = Single Compare Single-Shot mode: initialize OCx pin high, compare event forces OCx pin low
001 = Single Compare Single-Shot mode: initialize OCx pin low, compare event forces OCx pin high
000 = Output compare channel is disabled
U-0
U-0
—
—
on alternate matches of OCxR and OCxRS
and OCxRS for one cycle
OCxCON1: OUTPUT COMPARE x CONTROL 1 REGISTER
Select”.
HCS = Hardware Clearable/Settable bit
W = Writable bit
‘1’ = Bit is set
OCSIDL
R/W-0
U-0
—
CY
)
R/W-0, HCS
OCTSEL2
OCFLT0
R/W-0
(2)
(2)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
TRIGMODE
OCTSEL1
(1)
R/W-0
R/W-0
OCTSEL0
OCM2
R/W-0
R/W-0
(1)
2010 Microchip Technology Inc.
x = Bit is unknown
OCM1
R/W-0
U-0
—
(1)
Section 10.4
OCM0
R/W-0
U-0
—
(1)
bit 8
bit 0
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