PIC24HJ12GP202-E/SO Microchip Technology, PIC24HJ12GP202-E/SO Datasheet - Page 49

• Manufacturer Part Number: PIC24HJ12GP202-E/SO
• Description: 12KB, Flash, 1024bytes-RAM, 40MIPS, 21I/O, 16-bit Family,nanoWatt 28 SOIC .300in
• Manufacturer: Microchip Technology
• Series: PIC® 24Hr

Specifications of PIC24HJ12GP202-E/SO

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164339 - MODULE SKT FOR PM3 28SOICDV164033 - KIT START EXPLORER 16 MPLAB ICD2
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.0
The Reset module combines all Reset sources and
controls the device Master Reset Signal, SYSRST. The
following is a list of device Reset sources:
• POR: Power-on Reset
• BOR: Brown-out Reset
• MCLR: Master Clear Pin Reset
• SWR: RESET Instruction
• WDTO: Watchdog Timer Reset
• CM: Configuration Mismatch Reset
• TRAPR: Trap Conflict Reset
• IOPUWR: Illegal Condition Device Reset
A simplified block diagram of the Reset module is
shown in Figure 6-1.
FIGURE 6-1:
© 2009 Microchip Technology Inc.
Note:
- Illegal Opcode Reset
- Uninitialized W Register Reset
- Security Reset
RESETS
This data sheet summarizes the features
of the PIC24HJ12GP201/202 families of
devices. It is not intended to be a compre-
hensive reference source. To complement
the information in this data sheet, refer to
the PIC24H Family Reference Manual,
“Section 8. Reset” (DS70229), which is
available from the Microchip web site
(www.microchip.com).
MCLR
V
DD
Uninitialized W Register
Configuration Mismatch
RESET SYSTEM BLOCK DIAGRAM
Regulator
RESET Instruction
Internal
Sleep or Idle
Module
Illegal Opcode
WDT
Trap Conflict
V
Detect
DD
Glitch Filter
Rise
Preliminary
BOR
POR
PIC24HJ12GP201/202
Any active source of Reset will make the SYSRST
signal active. On system Reset, some of the registers
associated with the CPU and peripherals are forced to
a known Reset state, and some are unaffected.
All types of device Reset set a corresponding status bit
in the RCON register to indicate the type of Reset (see
Register 6-1).
All bits that are set, with the exception of the POR bit
(RCON<0>), are cleared during a POR event. The user
application can set or clear any bit at any time during
code execution. The RCON bits only serve as status
bits. Setting a particular Reset status bit in software
does not cause a device Reset to occur.
The RCON register also has other bits associated with
the Watchdog Timer and device power-saving states.
The function of these bits is discussed in other sections
of this data sheet.
Note:
Note:
Refer to the specific peripheral section or
Section 3.0 “CPU” of this manual for
register Reset states.
The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset is meaningful.
SYSRST
DS70282D-page 47