S29AL008J70BFI013 Spansion Inc., S29AL008J70BFI013 Datasheet - Page 30

• Manufacturer Part Number: S29AL008J70BFI013
• Description: IC 8M FLASH MEMORY
• Manufacturer: Spansion Inc.

Specifications of S29AL008J70BFI013

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 70ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 20/19Bit
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: FBGA
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 1M/512K
• Supply Current: 12mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Compliant

10.7
30
Chip Erase Command Sequence
Note
See
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical erase. The system is not required to provide any
controls or timings during these operations.
for the chip erase command sequence.
Any commands written to the chip during the Embedded Erase algorithm are ignored. Note that a hardware
reset during the chip erase operation immediately terminates the operation. The Chip Erase command
sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity.
The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. See
Operation Status on page 34
complete, the device returns to reading array data and addresses are no longer latched.
Figure 10.2 on page 32
on page 45
Table 10.1 on page 33
for parameters, and
for program command sequence.
illustrates the algorithm for the erase operation. See
for information on these status bits. When the Embedded Erase algorithm is
Increment Address
Figure 17.6 on page 46
Figure 10.1 Program Operation
S29AL008J
in progress
Table 10.1 on page 33
Embedded
algorithm
D a t a
Program
No
S h e e t
for timing diagrams.
Command Sequence
Write Program
Last Address?
Programming
from System
Verify Data?
Completed
Data Poll
START
Yes
Yes
shows the address and data requirements
S29AL008J_00_09 February 23, 2010
No
Erase/Program Operations
Write