SST38VF6401-90-5I-EKE Microchip Technology, SST38VF6401-90-5I-EKE Datasheet - Page 2

• Manufacturer Part Number: SST38VF6401-90-5I-EKE
• Description: 2.7V To 3.6V 64Mbit Pm Parallel Advanced MPF+ 48 TSOP 12x20 Mm TRAY
• Manufacturer: Microchip Technology

Specifications of SST38VF6401-90-5I-EKE

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 64M (4M x 16)
• Speed: 90ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TFSOP (0.472", 12.0mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Data Sheet
These devices also improve flexibility while lowering the
cost for program, data, and configuration storage applica-
tions. The SuperFlash technology provides fixed Erase and
Program times, independent of the number of Erase/Pro-
gram cycles that have occurred. Therefore, the system soft-
ware or hardware does not have to be modified or de-rated
as is necessary with alternative flash technologies, whose
Erase and Program times increase with accumulated
Erase/Program cycles.
The SST38VF6401/6402/6403/6404 also offer flexible data
protection features. Applications that require memory pro-
tection from program and erase operations can use the
Boot Block, Individual Block Protection, and Advanced Pro-
tection features. For applications that require a permanent
solution, the Irreversible Block Locking feature provides
permanent protection for memory blocks.
To meet high-density, surface mount requirements, the
SST38VF6401/6402/6403/6404 devices are offered in 48-
lead TSOP and 48-ball TFBGA packages. See Figures 2
and 3 for pin assignments and Table 7 for pin descriptions.
DEVICE OPERATION
The memory operations functions of these devices are initi-
ated using commands written to the device using standard
microprocessor Write sequences. A command is written by
asserting WE# low while keeping CE# low. The address
bus is latched on the falling edge of WE# or CE#, which-
ever occurs last. The data bus is latched on the rising edge
of WE# or CE#, whichever occurs first.
The SST38VF6401/6402/6403/6404 also have the Auto
Low Power mode which puts the device in a near-standby
mode after data has been accessed with a valid Read
operation. This reduces the I
typically 4 mA to typically 3 µA. The Auto Low Power mode
reduces the typical I
mA/MHz of Read cycle time. The device requires no
access time to exit the Auto Low Power mode after any
address transition or control signal transition used to initiate
another Read cycle. The device does not enter Auto-Low
Power mode after power-up with CE# held steadily low,
until the first address transition or CE# is driven high.
Read
The Read operation of the SST38VF6401/6402/6403/
6404 is controlled by CE# and OE#, both of which have
to be low for the system to obtain data from the outputs.
CE# is used for device selection. When CE# is high, the
chip is deselected and only standby power is consumed.
OE# is the output control and is used to gate data from
the output pins. The data bus is in high impedance state
©2009 Silicon Storage Technology, Inc.
DD
active read current to the range of 2
DD
SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404
active read current from
64 Mbit (x16) Advanced Multi-Purpose Flash Plus
2
when either CE# or OE# is high. Refer to Figure 5, the
Read cycle timing diagram, for further details.
Page Read
The Page Read operation utilizes an asynchronous
method that enables the system to read data from the
SST38VF6401/6402/6403/6404 at a faster rate. This oper-
ation allows users to read a four-word page of data at an
average speed of 41.25 ns per word.
In Page Read, the initial word read from the page requires
T
page require only T
the same address bits, A
page. Address bits A
read the words within the page.
The Page Read operation of the SST38VF6401/6402/
6403/6404 is controlled by CE# and OE#. Both CE# and
OE# must be low for the system to obtain data from the
output pins. CE# controls device selection. When CE# is
high, the chip is deselected and only standby power is con-
sumed. OE# is the output control and is used to gate data
from the output pins. The data bus is in high impedance
state when either CE# or OE# is high. Refer to Figure 6,
the Page Read cycle timing diagram, for further details.
Word-Program Operation
The SST38VF6401/6402/6403/6404 can be programmed
on a word-by-word basis. Before programming, the sector
where the word exists must be fully erased. The Program
operation is accomplished in three steps. The first step is the
three-byte load sequence for Software Data Protection. The
second step is to load word address and word data. During
the Word-Program operation, the addresses are latched on
the falling edge of either CE# or WE#, whichever occurs last.
The data is latched on the rising edge of either CE# or WE#,
whichever occurs first. The third step is the internal Program
operation which is initiated after the rising edge of the fourth
WE# or CE#, whichever occurs first. The Program operation,
once initiated, will be completed within 10 µs. See Figures 7
and 8 for WE# and CE# controlled Program operation timing
diagrams and Figure 24 for flowcharts.
During the Program operation, the only valid reads are
Data# Polling, Toggle Bits, and RY/BY#. During the internal
Program operation, the host is free to perform additional
tasks. Any commands issued during the internal Program
operation are ignored. During the command sequence,
WP# should be statically held high or low.
When programming more than a few words, SST recom-
mends Write-Buffer Programming.
ACC
to be valid, while the remaining three words in the
PACC
1
and A
21
. All four words in the page have
-A
2
0
, which are used to select the
are toggled, in any order, to
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