SST38VF6401-90-5I-EKE Microchip Technology, SST38VF6401-90-5I-EKE Datasheet - Page 5

• Manufacturer Part Number: SST38VF6401-90-5I-EKE
• Description: 2.7V To 3.6V 64Mbit Pm Parallel Advanced MPF+ 48 TSOP 12x20 Mm TRAY
• Manufacturer: Microchip Technology

Specifications of SST38VF6401-90-5I-EKE

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 64M (4M x 16)
• Speed: 90ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TFSOP (0.472", 12.0mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

64 Mbit (x16) Advanced Multi-Purpose Flash Plus
SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404
The SST38VF6401/6402/6403/6404 also provide a RY/
BY# signal. This signal indicates the status of a Program or
Erase operation.
If a Program or Erase operation is attempted on a pro-
tected sector or block, the operation will abort. After the
device initiates an abort, the corresponding Write Opera-
tion Status Detection Bits will stay active for approximately
200ns (program or erase) before the device returns to read
mode.
For the status of these bits during a Write operation, see
Table 1.
Data# Polling (DQ
When the SST38VF6401/6402/6403/6404 are in an inter-
nal Program operation, any attempt to read DQ
duce the complement of true data. For a Program Buffer-
to-Flash operation, DQ7 is the complement of the last
word loaded in the Write-Buffer using the Write-to-Buffer
command. Once the Program operation is completed,
DQ
may have valid data immediately following the completion
of an internal Write operation, the remaining data outputs
may still be invalid. Valid data on the entire data bus will
appear in subsequent successive Read cycles after an
interval of 1 µs.
During an internal Erase operation, any attempt to read
DQ
is completed, DQ
valid after the rising edge of fourth WE# (or CE#) pulse for
Program operation. For Sector-, Block- or Chip-Erase, the
Data# Polling is valid after the rising edge of sixth WE# (or
CE#) pulse. See Figure 11 for Data# Polling timing dia-
gram and Figure 26 for a flowchart.
TABLE 1: Write Operation Status
©2009 Silicon Storage Technology, Inc.
Status
Normal
Operation
Erase-Suspend
Mode
Program Buffer-
to-Flash
1. DQ
2. RY/BY# is an open drain pin. RY/BY# is high in Read mode, and Read in Erase-Suspend mode.
3. During a Program Buffer-to-Flash operation, the datum on the DQ
7
7
will produce a ‘0’. Once the internal Erase operation
will produce valid data. Note that even though DQ
Buffer using the Write-to-Buffer command.
7
and DQ
2
7
require a valid address when reading status information.
will produce a ‘1’. The Data# Polling is
Standard Program
Standard Erase
Read from Erase-Suspended
Sector/Block
Read from Non- Erase-
Suspended Sector/Block
Program
Busy
Abort
7
)
7
will pro-
DQ
0
1
Data
DQ
DQ
DQ
DQ
7
7
7
7
#
#
#
#
7
3
3
1
7
5
Toggle
Toggle
No toggle
Data
Toggle
Toggle
Toggle
7
pin is the complement of DQ
Toggle Bits (DQ
During the internal Program or Erase operation, any con-
secutive attempts to read DQ
and ‘0’s, i.e., toggling between ‘1’ and ‘0’. When the internal
Program or Erase operation is completed, the DQ
stop toggling, and the device is then ready for the next
operation. For Sector-, Block-, or Chip-Erase, the toggle bit
(DQ
pulse. DQ
on an Erase-Suspended Sector or Block. If Program oper-
ation is initiated in a sector/block not selected in Erase-Sus-
pend mode, DQ
An additional Toggle Bit is available on DQ
used in conjunction with DQ
sector or block is being actively erased or erase-sus-
pended. Table 1 shows detailed bit status information. The
Toggle Bit (DQ
WE# (or CE#) pulse of Write operation. See Figure 12 for
Toggle Bit timing diagram and Figure 26 for a flowchart.
DQ
If an operation aborts during a Write-to-Buffer or Program
Buffer-to-Flash operation, DQ
‘0’, issue the Write-to-Buffer Abort Reset command to exit
the abort state. A power-off/power-on cycle or a Hardware
Reset (RST# = 0) will also clear DQ
RY/BY#
The RY/BY# pin can be used to determine the status of a
Program or Erase operation. The RY/BY# pin is valid after
the rising edge of the final WE# pulse in the command
sequence. If RY/BY# = 0, then the device is actively pro-
gramming or erasing. If RY/BY# = 1, the device is in Read
mode. The RY/BY# pin is an open drain output pin. This
means several RY/BY# can be tied together with a pull-up
resistor to V
DQ
1
6
6
) is valid after the rising edge of sixth WE# (or CE#)
No Toggle
Toggle
Toggle
Data
N/A
N/A
N/A
6
will be set to ‘1’ if a Read operation is attempted
DD..
DQ
2
6
) is valid after the rising edge of the last
will toggle.
2
6
1
and DQ
7
of the last word loaded in the Write-
0
N/A
N/A
Data
N/A
0
1
6
2
1
to check whether a particular
)
6
is set to ‘1’. To reset DQ
will produce alternating ‘1’s
DQ
1
1
.
S71309-05-000
2
0
0
1
1
0
0
0
, which can be
RY/BY#
Data Sheet
6
T1.0 1309
bit will
2
07/09
1
to