STK12C68-SF25I Cypress Semiconductor Corp, STK12C68-SF25I Datasheet
STK12C68-SF25I
Specifications of STK12C68-SF25I
Related parts for STK12C68-SF25I
STK12C68-SF25I Summary of contents
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... Cypress Semiconductor Corporation Document Number: 001-51027 Rev Kbit ( AutoStore nvSRAM Functional Description The Cypress STK12C68 is a fast static RAM with a nonvolatile element in each memory cell. The embedded nonvolatile elements incorporate QuantumTrap technology producing the world’s most reliable nonvolatile memory. The SRAM provides unlimited read and write cycles, while independent nonvolatile data resides in the highly reliable QuantumTrap cell ...
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... SRAM Read Cycle .................................................... 10 SRAM Write Cycle ..................................................... 12 AutoStore or Power Up RECALL .................................. 14 Software Controlled STORE/RECALL Cycle................ 15 Hardware STORE Cycle ................................................. 16 Switching Waveform ...................................................... 16 Part Numbering Nomenclature ...................................... 17 Ordering Information ...................................................... 17 Package Diagrams .......................................................... 18 Document History Page ................................................. 23 Sales, Solutions, and Legal Information ...................... 24 Worldwide Sales and Design Support ....................... 24 Products .................................................................... 24 STK12C68 Page [+] Feedback ...
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... When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal pull up resistor keeps this pin high if not connected (connection optional). V Power Supply AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM CAP to nonvolatile elements. Document Number: 001-51027 Rev. *D Figure 1. 28-Pin SOIC/DIP and LLC Description STK12C68 Page [+] Feedback ...
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... SRAM. In addition, it provides unlimited RECALL opera- tions from the nonvolatile cells and up to one million STORE operations. SRAM Read The STK12C68 performs a Read cycle whenever CE and OE are LOW while WE and HSB are HIGH. The address specified on pins A determines the 8,192 data bytes accessed. When the 0– ...
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... RECALL request is latched. When V RESET once again exceeds the sense voltage of V cycle is automatically initiated and takes t If the STK12C68 Write state at the end of power up RECALL, the SRAM data is corrupted. To help avoid this situation Kohm resistor is connected either between WE and system V ...
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... Write is inhibited until a negative transition detected. This protects against inadvertent writes during power up or brown out conditions. Noise Considerations The STK12C68 is a high speed memory. It must have a high frequency bypass capacitor of approximately 0.1 µF connected between V and V using leads and traces that are as short ...
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... Read SRAM 0x0F0F Nonvolatile STORE H 0x0000 Read SRAM 0x1555 Read SRAM 0x0AAA Read SRAM 0x1FFF Read SRAM 0x10F0 Read SRAM 0x0F0E Nonvolatile RECALL STK12C68 I/O Power Output High Z Standby [3] Output Data Active Input Data Active [1] Output High Z I CC2 [2, 3] Output Data ...
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... Standby current level after = Max, V < V < Max, V < V < Max, V < V < > – STK12C68 or HSB .......................–0.5V to Vcc + 0.5V 0-7 Ambient Temperature V CC 0°C to +70°C 4.5V to 5.5V -40°C to +85°C 4.5V to 5.5V Min Max Commercial 1.5 Industrial 2.5 ...
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... Document Number: 001-51027 Rev. *D [6] Test Conditions = 25° MHz 3 [6] 28-PDIP 28-SOIC (300 mil) 46.55 45.16 27.95 31.62 Figure 6. AC Test Loads 5.0V Output R2 512Ω STK12C68 Min Unit 100 Years 1,000 Max 8 7 28-PDIP 28-CDIP 28-LCC (600 mil) 55.84 46.1 95.31 25.74 5.01 9.01 R1 963Ω ...
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... Output Disable to Output Inactive HZOE GHQZ [ Chip Enable to Power Active PU ELICCH [ Chip Disable to Power Standby PD EHICCL Switching Waveforms Figure 7. SRAM Read Cycle 1: Address Controlled Figure 8. SRAM Read Cycle 2: CE and OE Controlled Document Number: 001-51027 Rev Description Min Max STK12C68 Unit Min Max Min Max ...
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... Switching Waveforms Notes 7. WE and HSB must be High during SRAM Read cycles. 8. Device is continuously selected with CE and OE both Low. 9. Measured ±200 mV from steady state output voltage. Document Number: 001-51027 Rev. *D STK12C68 Page [+] Feedback ...
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... HSB must be high during SRAM Write cycles. 12 must be greater than V during address transitions. IH Document Number: 001-51027 Rev Description Min Max [11, 12 SCE PWE DATA VALID t HZWE HIGH IMPEDANCE [11, 12 SCE PWE DATA VALID HIGH IMPEDANCE STK12C68 Unit Min Max Min Max LZWE Page [+] Feedback ...
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... Document Number: 001-51027 Rev. *D Description Rise Time HSB Low SWITCH Figure 11. AutoStore/Power Up RECALL . SWITCH . If an SRAM Write has not taken place since the last nonvolatile cycle, HSB is released and no store SWITCH STK12C68 STK12C68 Unit Min Max μs 550 10 ms μs 1 4.0 4 ...
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... The software sequence is clocked on the falling edge of CE without involving OE (double clocking aborts the sequence). 18. The six consecutive addresses must be read in the order listed in Document Number: 001-51027 Rev. *D [18 Description Min Max DATA VALID Table 1 on page 7. WE must be HIGH during all six consecutive cycles. STK12C68 Unit Min Max Min Max μ [18 ...
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... Hardware STORE Pulse Width PHSB HLHX t Hardware STORE Low to STORE Busy HLBL Switching Waveform Note 19 only applicable after t is complete. DHSB STORE Document Number: 001-51027 Rev. *D Description Figure 13. Hardware STORE Cycle STK12C68 STK12C68 Unit Min Max 10 ms 700 300 ns Page [+] Feedback ...
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... STK12C68 - Ordering Information These parts are not recommended for new designs. They are in production to support ongoing production programs only. Speed (ns) Ordering Code 25 STK12C68-SF25TR STK12C68-SF25 STK12C68-SF25ITR STK12C68-SF25I STK12C68-PF25I STK12C68-WF25I 45 STK12C68-SF45TR STK12C68-SF45 STK12C68-SF45ITR STK12C68-SF45I STK12C68-C45I All parts are Pb-free. The above table contains Final information. Contact your local Cypress sales representative for availability of these parts Document Number: 001-51027 Rev ...
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... Package Diagrams Document Number: 001-51027 Rev. *D Figure 14. 28-Pin (330 Mil) SOIC (51-85058) STK12C68 51-85058 *B Page [+] Feedback ...
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... Package Diagrams (continued) Document Number: 001-51027 Rev. *D Figure 15. 28-Pin (300 Mil) PDIP (51-85014) STK12C68 51-85014 *E Page [+] Feedback ...
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... Package Diagrams (continued) Document Number: 001-51027 Rev. *D Figure 16. 28-Pin (600 Mil) PDIP (51-85017) STK12C68 51-85017 *D Page [+] Feedback ...
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... Package Diagrams (continued) Figure 17. 28-Pin (300 Mil) Side Braze DIL (001-51695) Document Number: 001-51027 Rev. *D STK12C68 001-51695 *A Page [+] Feedback ...
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... Package Diagrams (continued) Document Number: 001-51027 Rev. *D Figure 18. 28-Pad (350 Mil) LCC (001-51696) STK12C68 001-51696 *A Page [+] Feedback ...
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... Document History Page Document Title: STK12C68 64 Kbit ( AutoStore nvSRAM Document Number: 001-51027 Orig. of Rev. ECN No. Change ** 2606744 GVCH *A 2826441 GVCH *B 3054694 GVCH *C 3189527 GVCH *D 3208949 GVCH Document Number: 001-51027 Rev. *D Submission Description of Change Date 01/30/2009 New data sheet 12/11/2009 Added following text in the Ordering Information section: “These parts are not recommended for new designs. In production to support ongoing pro- duction programs only.” ...
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... Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-51027 Rev. *D All products and company names mentioned in this document may be the trademarks of their respective holders. cypress.com/go/plc Revised March 30, 2011 STK12C68 PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 ...