STK12C68-SF25I Cypress Semiconductor Corp, STK12C68-SF25I Datasheet - Page 6

• Manufacturer Part Number: STK12C68-SF25I
• Description: STK12C68-SF25I
• Manufacturer: Cypress Semiconductor Corp
• Type: NVSRAMr

Specifications of STK12C68-SF25I

• Format - Memory: RAM
• Memory Type: NVSRAM (Non-Volatile SRAM)
• Memory Size: 64K (8K x 8)
• Speed: 25ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (8.69mm width)
• Word Size: 8b
• Organization: 8Kx8
• Density: 64Kb
• Interface Type: Parallel
• Access Time (max): 25ns
• Operating Supply Voltage (typ): 5V
• Package Type: SOIC
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Operating Temp Range: -40C to 85C
• Pin Count: 28
• Mounting: Surface Mount
• Supply Current: 85mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Software RECALL
Data is transferred from the nonvolatile memory to the SRAM by
a software address sequence. A software RECALL cycle is
initiated with a sequence of Read operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE controlled Read operations is
performed:
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared; then, the nonvolatile information is transferred into the
SRAM cells. After the t
ready for Read and Write operations. The RECALL operation
does not alter the data in the nonvolatile elements. The nonvol-
atile data can be recalled an unlimited number of times.
Data Protection
The STK12C68 protects data from corruption during low voltage
conditions by inhibiting all externally initiated STORE and Write
operations. The low voltage condition is detected when V
less than V
and WE are low) at power up after a RECALL or after a STORE,
the Write is inhibited until a negative transition on CE or WE is
detected. This protects against inadvertent writes during power
up or brown out conditions.
Noise Considerations
The STK12C68 is a high speed memory. It must have a high
frequency bypass capacitor of approximately 0.1 µF connected
between V
as possible. As with all high speed CMOS ICs, careful routing of
power, ground, and signals reduce circuit noise.
Hardware Protect
The STK12C68 offers hardware protection against inadvertent
STORE operation and SRAM Writes during low voltage condi-
tions. When V
operations and SRAM Writes are inhibited. AutoStore can be
completely disabled by tying VCC to ground and applying +5V to
V
are only initiated by explicit request using either the software
sequence or the HSB pin.
Low Average Active Power
CMOS technology provides the STK12C68 the benefit of
drawing significantly less current when it is cycled at times longer
than 50 ns.
Read or Write cycle time. Worst case current consumption is
shown for both CMOS and TTL input levels (commercial temper-
ature range, VCC = 5.5V, 100% duty cycle on chip enable). Only
standby current is drawn when the chip is disabled. The overall
average current drawn by the STK12C68 depends on the
following items:
Document Number: 001-51027 Rev. *D
1. Read address 0x0000, Valid READ
2. Read address 0x1555, Valid READ
3. Read address 0x0AAA, Valid READ
4. Read address 0x1FFF, Valid READ
5. Read address 0x10F0, Valid READ
6. Read address 0x0F0E, Initiate RECALL cycle
CAP
. This is the AutoStore Inhibit mode; in this mode, STOREs
CC
SWITCH
Figure 4
and V
CAP
. If the STK12C68 is in a Write mode (both CE
<V
SS,
shows the relationship between I
SWITCH
using leads and traces that are as short
RECALL
, all externally initiated STORE
cycle time, the SRAM is again
CC
CC
and
is
■
■
■
■
■
■
■
Figure 4. Current Versus Cycle Time (Read)
Figure 5. Current Versus Cycle Time (Write)
Preventing Store
The STORE function is disabled by holding HSB high with a
driver capable of sourcing 30 mA at a V
because it must overpower the internal pull down device. This
device drives HSB LOW for 20 μs at the onset of a STORE.
When the STK12C68 is connected for AutoStore operation
(system V
and V
attempts to pull HSB LOW. If HSB does not actually get below
V
attempt.
IL
The duty cycle of chip enable
The overall cycle rate for accesses
The ratio of Reads to Writes
CMOS versus TTL input levels
The operating temperature
The V
I/O loading
, the part stops trying to pull HSB LOW and abort the STORE
CC
CC
crosses V
CC
level
connected to V
SWITCH
CC
on the way down, the STK12C68
and a 68 μF capacitor on V
OH
STK12C68
of at least 2.2V,
Page 6 of 23
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