SY89429VJZ Micrel Inc, SY89429VJZ Datasheet - Page 5

• Manufacturer Part Number: SY89429VJZ
• Description: 5V/3.3V Programmable Frequency Synthesizer (25-400MHz) ( )
• Manufacturer: Micrel Inc
• Series: Precision Edge®r
• Type: Frequency Synthesizerr

Specifications of SY89429VJZ

• Pll: Yes
• Input: Crystal
• Output: PECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:1
• Differential - Input:output: No/Yes
• Frequency - Max: 800MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 5.25 V
• Operating Temperature: 0°C ~ 75°C
• Mounting Type: Surface Mount
• Package / Case: 28-LCC (J-Lead)
• Frequency-max: 10.7GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 576-2559; SY89429VJZ

Micrel, Inc.
basis of its frequency reference. The output of the reference
oscillator is divided by eight before being sent to the phase
detector. With a 16MHz crystal, this provides a reference frequency
of 2MHz.
800MHz. Its output is scaled by a divider that is configured by
either the serial or parallel interfaces. The output of this loop
divider is also applied to the phase detector.
frequency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too
high or too low) the PLL will not achieve loop lock. External loop
filter components are utilized to allow for optimal phase jitter
performance.
divider before being sent to the PECL output driver. The output
divider is configured through either the serial or the parallel
interfaces and can provide one of four divider ratios (2, 4, 8 or 16).
This divider extends the performance of the part while providing
a 50% duty cycle.
and is capable of driving a pair of transmission lines terminated
M9999-011106
[e-mail] or [phone]
FUNCTIONAL DESCRIPTION
WITH 16MHZ INPUT
The internal oscillator uses the external quartz crystal as the
The VCO, within the PLL, operates over a range of 400–
The phase detector and loop filter force the VCO output
The output of the VCO is also passed through an output
The output driver is driven differentially from the output divider
VCO Frequency
(MHz)
400
402
404
406
794
796
798
800
•
•
•
M Count
200
201
202
203
397
398
399
400
•
•
•
256
M8
0
0
0
0
1
1
1
1
•
•
•
128
M7
1
1
1
1
1
1
1
1
•
•
•
M6
64
1
1
1
1
0
0
0
0
•
•
•
5
in 50Ω to V
is provided by a dedicated power pin (V
induced jitter.
The parallel interface uses the values at the M[8:0] and N[1:0]
inputs to configure the internal counters. Normally, upon
system reset, the /P
after power becomes valid. With S
LOW-to-HIGH transition of /P
captured. The parallel interface has priority over the serial
interface. Internal pull-up resistors are provided on the M[8:0]
and N[1:0] inputs to reduce component count.
register scheme. The register shifts once per rising edge of the
S
hold timing as specified in the AC parameters section of this data-
sheet. With /P
capture the value in the shift register on the HIGH-to-LOW edge
of the S
information.
controlled by the T[2:0] bits in the serial data stream. See the
programming subsection of this data sheet for more information.
_CLOCK
The configuration logic has two sections: serial and parallel.
The serial interface logic is implemented with a 14-bit shift
The TEST output reflects various internal node values and is
M5
32
0
0
0
0
0
0
0
0
•
•
•
_LOAD
input. The serial input S
CC
–2 volts. The positive reference for the output driver
_LOAD
input. See the programming section for more
M4
16
0
0
0
0
0
0
0
1
•
•
•
_LOAD
held HIGH, the configuration latches will
M3
8
1
1
1
1
1
1
1
0
•
•
•
input is held LOW until some time
_LOAD
_DATA
M2
_LOAD
4
0
0
0
0
1
1
1
0
•
•
•
, the parallel inputs are
CC_OUT
must meet set-up and
held LOW, on the
Precision Edge
) to reduce noise
M1
2
0
0
1
1
0
1
1
0
•
•
•
SY89429V
M0
1
0
1
0
1
1
0
1
0
•
•
•
®