8501501XA Intersil, 8501501XA Datasheet - Page 17

• Manufacturer Part Number: 8501501XA
• Manufacturer: Intersil

Specifications of 8501501XA

• Transmitter And Receiver Fifo Counter: No
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Mounting: Through Hole
• Supply Current: 4mA
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Not Compliant

UART Timing Characterization
NOTES:
1. TBRE bit D6 in USR is updated each time TBRE changes state.
2. A. With TR initially empty, TCLTH(TBRE) occurs from the 4th falling edge of CO(BRG) after WR goes high.
3. A. With TR (Transmitter Register) initially empty, TDTX occurs from the 5th falling edge of CO(BRG) after WR goes high.
4. TCTHX is time before end of last Stop bit by which CTS must be inactive (high) to prevent transmission of the character waiting in TBR.
5. With CTS high (disable transmit) and TBR full, TCLTH(TBRE) occurs from the 4th falling edge of CO(BRG) after CTS goes low.
6. With CTS high (disable transmit) and TBR full, TDTX occurs from the 5th falling edge of CO(BRG) after CTS goes low.
B. With TR initially full, TCLTH(TBRE) occurs from the trailing edge of the 15th CO(BRG) in the last Stop bit provided WR went high by the
B. With TR initially full, TDTX occurs from the trailing edge of the 16th CO(BRG) in the last Stop bit provided WR went high by the trailing edge
trailing edge of the 12th CO(BRG) in the last Stop bit.
of the 12th CO(BRG) in the last Stop bit.
CO(BRG)
INTR
SDI
RD
DR
NOTE 1
NOTE 2
TDRH
(25)
11
17
12
TIHF
(21)
(Continued)
13
LAST STOP BIT
FIGURE 19. RECEIVE TIMING
RBR
TRLDL
(26)
14
82C52
82C52
15
USR
16
TRLIL
(23)
START BIT / IDLE
1/I
2/I
3/I
April 26, 2006
FN2950.3