SAA7105E/V1/G NXP Semiconductors, SAA7105E/V1/G Datasheet

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SAA7105E/V1/G

Manufacturer Part Number
SAA7105E/V1/G
Description
Video ICs PC-DENC
Manufacturer
NXP Semiconductors
Datasheet

Specifications of SAA7105E/V1/G

Adc/dac Resolution
10b
Screening Level
Commercial
Package Type
LBGA
Pin Count
156
Lead Free Status / RoHS Status
Compliant
Other names
SAA7105E/V1/G,557

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Manufacturer
Quantity
Price
Part Number:
SAA7105E/V1/G,518
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Part Number:
SAA7105E/V1/G,557
Manufacturer:
NXP Semiconductors
Quantity:
10 000
1. General description
2. Features
The SAA7104E; SAA7105E is an advanced next-generation video encoder which
converts PC graphics data at maximum 1280
interlaced) to PAL (50 Hz) or NTSC (60 Hz) video signals. A programmable scaler and
anti-flicker filter (maximum 5 lines) ensures properly sized and flicker-free TV display as
CVBS or S-video output.
Alternatively, the three Digital-to-Analog Converters (DACs) can output RGB signals
together with a TTL composite sync to feed SCART connectors.
When the scaler/interlacer is bypassed, a second VGA monitor can be connected to the
RGB outputs and separate H and V-syncs as well, thereby serving as an auxiliary monitor
at maximum 1280
can provide Y, P
The device includes a sync/clock generator and on-chip DACs.
All inputs intended to interface to the host graphics controller are designed for low-voltage
signals between down to 1.1 V and up to 3.6 V.
SAA7104E; SAA7105E
Digital video encoder
Rev. 02 — 23 December 2005
Digital PAL/NTSC encoder with integrated high quality scaler and anti-flicker filter for
TV output from a PC
Supports Intel Digital Video Out (DVO) low voltage interfacing to graphics controller
27 MHz crystal-stable subcarrier generation
Maximum graphics pixel clock 85 MHz at double edged clocking, synthesized on-chip
or from external source
Programmable assignment of clock edge to bytes (in double edged mode)
Synthesizable pixel clock (PIXCLK) with minimized output jitter, can be used as
reference clock for the VGC, as well
PIXCLK output and bi-phase PIXCLK input (VGC clock loop-through possible)
Hot-plug detection through dedicated interrupt pin
Supported VGA resolutions for PAL or NTSC legacy video output up to 1280
graphics data at 60 Hz or 50 Hz frame rate
Supported VGA resolutions for HDTV output up to 1920
data at 60 Hz or 50 Hz frame rate
Three Digital-to-Analog Converters (DACs) at 27 MHz sample rate for CVBS (BLUE,
C
10-bit resolution
Non-Interlaced (NI) C
B
), VBS (GREEN, CVBS) and C (RED, C
B
and P
1024 resolution/60 Hz (PIXCLK < 85 MHz). Alternatively this port
R
B
signals for HDTV monitors.
-Y-C
R
or RGB input at maximum 4 : 4 : 4 sampling
R
) (signals in parenthesis are optional); all at
1024 resolution (optionally 1920
Product data sheet
1080 interlaced graphics
1024
1080

Related parts for SAA7105E/V1/G

SAA7105E/V1/G Summary of contents

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SAA7104E; SAA7105E Digital video encoder Rev. 02 — 23 December 2005 1. General description The SAA7104E; SAA7105E is an advanced next-generation video encoder which converts PC graphics data at maximum 1280 interlaced) to PAL (50 Hz) or NTSC (60 Hz) ...

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Philips Semiconductors Downscaling and upscaling from 400 % Optional interlaced C Optional non-interlaced RGB output to drive second VGA monitor (bypass mode with maximum 85 MHz) 3 bytes Support for hardware cursor HDTV up to 1920 sync ...

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Philips Semiconductors 4. Ordering information Table 2: Type number Package SAA7104E SAA7105E SAA7104E_SAA7105E_2 Product data sheet Ordering information Name Description LBGA156 plastic low profile ball grid array package; 156 balls; body 15 Rev. 02 — 23 December 2005 SAA7104E; SAA7105E ...

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DDA1 DDA2 DDA3 DDA4 SSA1 A10, B9 C9, D9 C1, C2, B1, B2, A2, B4, B3, A3, F3, H1, H2, H3 PD11 to INPUT PD0 FORMATTER UPSAMPLING DECIMATOR HORIZONTAL ...

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Philips Semiconductors 6. Pinning information 6.1 Pinning Fig 2. Pin configuration Table 3: Pin A10 SAA7104E_SAA7105E_2 Product data sheet ball A1 ...

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Philips Semiconductors Table 3: Pin E12 6.2 Pin description Table 4: Symbol PD7 PD4 TRST XTALI XTALO DUMP V SSA2 RSET V DDA1 PD9 PD8 PD5 PD6 TDI V DDA2 V DDA4 V SSA1 ...

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Philips Semiconductors Table 4: Symbol GREEN_VBS_CVBS C7 RED_CR_C_CVBS TDO RESET TMS V DDD2 V DDD3 V DDD4 V DDA3 VSM HSM_CSYNC TCK SCL HSVGC reserved VSVGC PIXCLKI PD3 V DDD1 TVD FSVGC SDA CBO PIXCLKO PD2 PD1 PD0 [1] Pin ...

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Philips Semiconductors 7. Functional description The digital video encoder encodes digital luminance and color difference signals (C -Y -Y-C R The SAA7104E; SAA7105E can be directly connected video graphics controller with a maximum resolution of ...

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Philips Semiconductors In order to display interlaced RGB signals through a euro-connector TV set, a separate digital composite sync signal (pin HSM_CSYNC) can be generated; it can be advanced periods of the 27 MHz crystal clock in ...

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Philips Semiconductors 7.2 Input formatter The input formatter converts all accepted PD input data formats, either RGB or Y common internal RGB or Y-C When double-edge clocking is used, the data is internally split into portions PPD1 and ...

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Philips Semiconductors For each direction, there are 2 registers controlling the position of the cursor, one controls the position of the ‘hot spot’, the other register controls the insertion position. The hot spot is the ‘tip’ of the pointer arrow. ...

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Philips Semiconductors If the SAA7104E; SAA7105E input data is in accordance with ‘ITU-R BT.656’ , the scaler enters another mode. In this event, XINC needs to be set to 2048 for a scaling factor of 1. With higher values, upscaling ...

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Philips Semiconductors 7.10 Oscillator and Discrete Time Oscillator (DTO) The master clock generation is realized MHz crystal oscillator, which can operate with either a fundamental wave crystal or a 3rd-harmonic crystal. The crystal clock supplies the DTO ...

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Philips Semiconductors Chrominance is modified in gain (programmable separately for C standard dependent burst is inserted, before baseband color signals are interpolated from a 6.75 MHz data rate MHz data rate. One of the interpolation stages can ...

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Philips Semiconductors 7.13 RGB processor This block contains a dematrix in order to produce RED, GREEN and BLUE signals to be fed to a SCART plug. Before Y, C difference signals and 2 times oversampling for luminance and 4 times ...

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Philips Semiconductors In Slave mode, the circuit accepts sync pulses on the bidirectional FSVGC (frame sync), VSVGC (vertical sync) and HSVGC (horizontal sync) pins: the polarities of the signals can be programmed. The frame sync signal is only necessary when ...

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Philips Semiconductors to insert certain values in the outgoing data stream at specified times. It can also be used to generate digital signals associated with time events. These can be used as digital horizontal and vertical synchronization signals on pins ...

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Philips Semiconductors The 4-bit index in the line count array points to the line type array. It holds entries (index 0 is not used), index 1 points to the first entry, index 2 to the second entry ...

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Philips Semiconductors Table 9: Example for set-up of the sync tables Sequence Comment Write to subaddress D0h 00 points to first entry of line count array (index generate 5 lines of line type index 2 (this is ...

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Philips Semiconductors 2 7.18 I C-bus interface 2 The I C-bus interface is a standard slave transceiver, supporting 7-bit slave addresses and 400 kbit/s guaranteed transfer rate. It uses 8-bit subaddressing with an auto-increment function. All registers are write and ...

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Philips Semiconductors The following Sections give the set of equations required to program the IC for the most common application: A post processor in Master mode with non-interlaced video input data. Some variables are defined below: • InPix: the number ...

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Philips Semiconductors TPclk = PCL = should be set according to Setting a lower value means that the internal pixel clock is higher and the data get sampled up. The difference may 640 with 320 pixels per ...

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Philips Semiconductors YIWGTO YIWGTE When YINC = 0 it sets the scaler to scaling factor 1. The initial weighting factors must not be set this case. YIWGTE may go negative. In this event, YINC should be added ...

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Philips Semiconductors Table 10: Color White Yellow Cyan Green Magenta Red Blue Black [1] Transformation 1.3707 1.7324 Table 11: Data slot control (example for format 0) SLOT 0 0 ...

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Philips Semiconductors Table 13 5-bit non-interlaced RGB Pin PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Table 14 5-bit non-interlaced RGB Pin ...

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Philips Semiconductors Table 16 8-bit interlaced C Pin PD4 PD3 PD2 PD1 PD0 Table 17: 8-bit non-interlaced index color Pin PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 ...

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Bit allocation map Table 19: Slave receiver (slave address 88h) Register function Subaddress (hexadecimal) Status byte (read only) 00 Null Common DAC adjust fi DAC adjust coarse 17 G DAC adjust coarse 18 B ...

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Table 19: Slave receiver (slave address 88h) …continued Register function Subaddress (hexadecimal) Gain U 5B Gain V 5C Gain U MSB, black level 5D Gain V MSB, blanking level 5E CCR, blanking level VBI 5F Null 60 Standard control 61 ...

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Table 19: Slave receiver (slave address 88h) …continued Register function Subaddress (hexadecimal) TTX even request vertical start 78 TTX even request vertical end 79 First active line 7A Last active line 7B TTX mode, MSB vertical 7C Null 7D Disable ...

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Table 19: Slave receiver (slave address 88h) …continued Register function Subaddress (hexadecimal) Weighting factor even 9E Weighting factor MSB 9F Vertical line skip A0 Blank enable for NI-bypass, A1 vertical line skip MSB Border color Y A2 Border color U ...

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Table 19: Slave receiver (slave address 88h) …continued Register function Subaddress (hexadecimal) Horizontal cursor position F9 Horizontal hot spot, MSB XCP FA Vertical cursor position FB Vertical hot spot, MSB YCP FC Input path control FD Cursor bit map FE ...

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Philips Semiconductors 2 8.2 I C-bus format control registers S 1000 1000 b. to the HD line count array (subaddress D0h) S 1000 1000 c. to cursor bit map (subaddress FEh) S 1000 1000 d. to color ...

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Philips Semiconductors Table 20: Code S Sr 1000 100X A Am SUBADDRESS DATA -------- P RAM ADDRESS [ the read/write control bit logic 0 is order to write logic 1 is order to read. ...

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Philips Semiconductors Table 22: Subaddress Bit 17h to 19h 17h 18h 19h Table 23: Bit MSMT[7:0] Table 24: Legend default value after reset. Bit and SAA7104E_SAA7105E_2 ...

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Philips Semiconductors Table 25: Legend default value after reset. Subaddress Bit 27h 26h Table 26: Legend default value after reset. Bit 7 and Table 27: Legend default value after ...

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Philips Semiconductors Table 28: Legend default value after reset. Subaddress Bit 2Ch 2Bh 2Ah Table 29: Legend default value after reset. Bit Symbol 7 VBSEN 6 CVBSEN1 R/W 5 CVBSEN0 R/W 4 CEN 3 ENCOFF 2 ...

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Philips Semiconductors Table 30: Legend default value after reset. Bit and 4 YFIL[1:0] R Table 31: Legend default value after reset. Bit Table ...

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Philips Semiconductors Table 33: Legend default value after reset. Bit Table 34: Legend default value after reset. Bit and 2 - SAA7104E_SAA7105E_2 Product ...

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Philips Semiconductors Table 34: Legend default value after reset. Bit 1 0 Table 35: Subaddress Bit 55h 56h 57h 58h 59h [1] In line 16; LSB first; all other bytes are not relevant for VPS. Table 36: Legend: ...

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Philips Semiconductors Table 37: Gain U and gain U MSB, black level registers, subaddresses 5Bh and 5Dh, bit description Subaddress Bit Symbol 5Bh GAINU[8:0] 5Dh BLCKL[5:0] [1] Variable gain for C ...

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Philips Semiconductors Table 39: Bit 7 and 6 CCRS[1: Table 40: Legend default value after reset. Bit SAA7104E_SAA7105E_2 Product data sheet CCR and blanking level VBI register, ...

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Philips Semiconductors Table 41: Legend default value after reset recommended value. Bit Symbol 7 RTCE BSTA[6:0] R/W Table 42: Subaddress Bit 66h 65h 64h 63h FSC [1] Examples: a) NTSC ...

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Philips Semiconductors Table 44: Legend default value after reset. Subaddress Bit 6Ch 6Dh [1] Values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed; increasing HTRIG decreases delays of all internally generated timing signals. ...

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Philips Semiconductors Table 46: Legend default value after reset. Bit 7 and 6 CCEN[1: Table 47: Subaddress Bit 70h 71h 72h [1] Values above 1715 (FISE = 1) or 1727 (FISE = 0) are ...

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Philips Semiconductors Table 49: Legend default value after reset and minimum value. Bit Symbol TTXHD[3:0] Table 50: Bit Symbol CSYNCA[4:0] R Table 51: Legend: ...

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Philips Semiconductors Table 54: Legend default value after reset. Bit Symbol TTXEVE[7:0] R/W Table 55: Bit Symbol FAL[7:0] Table 56: Bit Symbol LAL[7:0] Table 57: Legend default ...

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Philips Semiconductors Table 58: Subaddress Bit 7Eh 7Fh [1] This bit mask is effective only if the lines are enabled by TTXOVS/TTXOVE and TTXEVS/TTXEVE. Table 59: Subaddress Bit 81h 82h 83h Table 60: Legend default value after reset. ...

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Philips Semiconductors Table 61: Legend default value after reset nominal value. Bit Table 62: Bit Table 63: Bit Table 64: Bit 7 to ...

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Philips Semiconductors Table 68: Bit and 0 YPIX[9:8] Table 69: Bit SAA7104E_SAA7105E_2 Product data sheet Scaler CTRL, MCB and YPIX register, subaddress 96h, bit description Symbol Access Value ...

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Philips Semiconductors Table 69: Bit Table 70: Bit Table 71: Bit Table 72: Bit Table 73: Bit SAA7104E_SAA7105E_2 Product data sheet Sync ...

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Philips Semiconductors Table 74: Bit Table 75: Bit Table 76: Bit Table 77: Bit Table 78: Bit Table 79: ...

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Philips Semiconductors Table 81: Bit Table 82: Bit Table 83: Data byte HLCA HLC HLT Table 84: Byte 0 1 Table 85: Data byte HLTA HLP Table 86: Byte SAA7104E_SAA7105E_2 ...

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Philips Semiconductors Table 87: Data byte HLPA HPD HPV Table 88: Byte Table 89: Data byte HPVA HPVE HHS HVS Table 90: Byte 0 1 Table 91: Bit Symbol ...

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Philips Semiconductors Table 92: Bit and 2 HLPPT[1:0] state of the HD pattern pointer after trigger 1 and 0 HLCT[9:8] Table 93: Bit Table 94: Bit and 2 ...

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Philips Semiconductors Table 97: Legend default value after reset. Bit 1 0 Table 98: Subaddress Bit F0h F1h F2h Table 99: Subaddress Bit F3h F4h F5h Table 100: Auxiliary cursor color R, G and B registers, subaddresses F6h ...

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Philips Semiconductors Table 103: Input path control register, subaddress FDh, bit description Bit Symbol 7 LUTOFF R/W 6 CMODE R/W 5 LUTL IF[2:0] 1 MATOFF R/W 0 DFOFF Table 104: Cursor bit map register, subaddress FEh, bit ...

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Philips Semiconductors 8.4 Slave transmitter Table 106: Status byte register, subaddress 00h, bit description Bit Symbol VER[2: CCRDO 3 CCRDE FSEQ 0 O_E Table 107: Slave transmitter (slave address 89h) Register function ...

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Philips Semiconductors Table 109: FIFO status register, subaddress 80h, bit description Bit Symbol Access Value Description IFERR 2 BFERR R 1 OVFL 0 UDFL G v (dB) (1) SCBW = 1. (2) SCBW = 0. ...

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Philips Semiconductors (1) SCBW = 1. (2) SCBW = 0. Fig 7. Chrominance transfer characteristic (dB) (1) CCRS[1:0] = 01. (2) CCRS[1:0] = 10. (3) CCRS[1:0] = 11. (4) CCRS[1:0] = 00. Fig 8. Luminance transfer characteristic ...

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Philips Semiconductors (1) CCRS[1: Fig 9. Luminance transfer characteristic 2 (excluding scaler) G (dB) Fig 10. Luminance transfer characteristic in RGB (excluding scaler) SAA7104E_SAA7105E_2 Product data sheet (dB ...

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Philips Semiconductors G (dB) Fig 11. Color difference transfer characteristic in RGB (excluding scaler) 9. Limiting values Table 110: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). All ground pins connected together and grounded (0 V); ...

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Philips Semiconductors 10. Thermal characteristics Table 111: Thermal characteristics Symbol Parameter R thermal resistance from junction to ambient th(j-a) [1] The overall R value can vary depending on the board layout. To minimize the effective R th(j-a) connected to the ...

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Philips Semiconductors Table 112: Characteristics …continued (typical values excluded); unless otherwise specified. amb Symbol Parameter Outputs V LOW-level output OL voltage V HIGH-level output OH voltage 2 I C-bus; pins SDA and SCL ...

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Philips Semiconductors Table 112: Characteristics …continued (typical values excluded); unless otherwise specified. amb Symbol Parameter Data and reference signal output timing C output load capacitance o(L) t output hold time to o(h)(gfx) graphics ...

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Philips Semiconductors PIXCLKO PIXCLKI PDn any output Fig 12. Input/output timing specification HSVGC Fig 13. Horizontal input timing HSVGC VSVGC Fig 14. Vertical input timing SAA7104E_SAA7105E_2 Product data sheet t HIGH t t d(CLKD HD;DAT t t o(d) ...

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Philips Semiconductors 11.1 Teletext timing Time t FD VBS output signal, such that it appears at t after the leading edge of the horizontal synchronization pulse. Time t PD TTXRQ_XCLKO2 in order to deliver TTX data. This delay is programmable ...

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Philips Semiconductors 12. Application information DVO 3.3 V digital supply supply 0.1 F 0.1 F DGND use one capacitor for each V DDD DDD1 DDD2 digital inputs and outputs V SSD1 DGND Fig 16. Application circuit ...

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Philips Semiconductors Fig 17. FLTR0, FLTR1 and FLTR2 of SAA7104E_SAA7105E_2 Product data sheet SAA7104E; SAA7105E C16 120 pF L2 2.7 H C10 C13 390 pF 560 pF AGND JP11 JP12 FIN FILTER 1 = byp. ll act. Figure 16 Rev. ...

Page 69

Philips Semiconductors SAA7104E SAA7105E A5 XTALI 27.00 MHz 4 With 3rd harmonic quartz. Crystal load = 8 pF. SAA7104E SAA7105E A5 XTALI 27.00 MHz clock c. With direct clock. Fig 18. Oscillator application 12.1 ...

Page 70

Philips Semiconductors By setting the reference currents of the DACs as shown in amplitudes can be achieved for all signal combinations assumed that in subaddress 16h, parameter DACF = 0000b, that means the fine adjustment for all DACs ...

Page 71

Philips Semiconductors 13. Test information 13.1 Boundary scan test The SAA7104E; SAA7105E has built-in logic and 5 dedicated pins to support boundary scan testing which allows board testing without special hardware (nails). The SAA7104E; SAA7105E follows the ‘IEEE Std. 1149.1 ...

Page 72

Philips Semiconductors used to verify component manufacturer, type and version number. The device identification register contains 32 bits, numbered where bit 31 is the most significant bit (nearest to TDI) and bit 0 is the least significant ...

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Philips Semiconductors 14. Package outline LBGA156: plastic low profile ball grid array package; 156 balls; body 1.05 mm ball A1 index area ...

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Philips Semiconductors 15. Soldering 15.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages ...

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Philips Semiconductors – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, ...

Page 76

Philips Semiconductors [4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, ...

Page 77

Philips Semiconductors 17. Data sheet status [1] Level Data sheet status Product status I Objective data Development II Preliminary data Qualification III Product data Production [1] Please consult the most recently issued data sheet before initiating or completing a design. ...

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Philips Semiconductors 22. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...

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