SAA7105E/V1/G-T NXP Semiconductors, SAA7105E/V1/G-T Datasheet
SAA7105E/V1/G-T
Specifications of SAA7105E/V1/G-T
Related parts for SAA7105E/V1/G-T
SAA7105E/V1/G-T Summary of contents
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DATA SHEET SAA7104E; SAA7105E Digital video encoder Product specification INTEGRATED CIRCUITS 2004 Mar 04 ...
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Philips Semiconductors Digital video encoder CONTENTS 1 FEATURES 2 GENERAL DESCRIPTION 3 QUICK REFERENCE DATA 4 ORDERING INFORMATION 5 BLOCK DIAGRAM 6 PINNING 7 FUNCTIONAL DESCRIPTION 7.1 Reset conditions 7.2 Input formatter 7.3 RGB LUT 7.4 Cursor insertion 7.5 RGB ...
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Philips Semiconductors Digital video encoder 1 FEATURES Digital PAL/NTSC encoder with integrated high quality scaler and anti-flicker filter for TV output from a PC Supports Intel Digital Video Out (DVO) low voltage interfacing to graphics controller 27 MHz crystal-stable subcarrier ...
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Philips Semiconductors Digital video encoder 2 GENERAL DESCRIPTION The SAA7104E; SAA7105E is an advanced next-generation video encoder which converts PC graphics data at maximum 1280 (optionally 1920 1080 interlaced) to PAL (50 Hz) or NTSC (60 Hz) video signals. A ...
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Acrobat reader. white to force landscape pages to be ... DDA1 DDA2 DDA3 DDA4 SSA1 A10, B9 ...
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Philips Semiconductors Digital video encoder 6 PINNING SYMBOL PIN PD7 A2 PD4 A3 TRST A4 XTALI A5 XTALO A6 DUMP A7 SSA2 RSET A9 V A10, B9, C9, D9 DDA1 PD9 B1 PD8 B2 PD5 B3 PD6 ...
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Philips Semiconductors Digital video encoder SYMBOL PIN VSM D7 HSM_CSYNC D8 TCK E1 SCL E2 HSVGC E3 reserved E12 VSVGC F1 PIXCLKI F2 PD3 DDD1 TVD F12 FSVGC G1 SDA G2 CBO G3 PIXCLKO G4 PD2 H1 ...
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Philips Semiconductors Digital video encoder Table 1 Pin assignment (top view PD7 PD4 TRST B PD9 PD8 PD5 PD6 C PD11 PD10 TTX_ TTXRQ_ SRES XCLKO2 D TDO RESET TMS V DDD2 V DDD3 V DDD4 ...
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Philips Semiconductors Digital video encoder handbook, halfpage 7 FUNCTIONAL DESCRIPTION The digital video encoder encodes digital luminance and colour difference signals (C -Y-C B into analog CVBS, S-video and, optionally, RGB or C -Y-C signals. NTSC M, PAL B/G and ...
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Philips Semiconductors Digital video encoder formats are “ITU-R BT.656” The 8-bit multiplexed C -Y (D1 format) compatible, but the SAV and EAV codes can be decoded optionally, when the device is operated in slave mode. For assignment of ...
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Philips Semiconductors Digital video encoder 7.3 RGB LUT The three 256 byte RAMs of this block can be addressed by three 8-bit wide signals, thus it can be used to build any transformation, e.g. a gamma correction for RGB signals. ...
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Philips Semiconductors Digital video encoder 7.5 RGB Y-C -C matrix B R RGB input signals to be encoded to PAL or NTSC are converted to the Y-C -C colour space in this block. The B R colour difference signals are ...
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Philips Semiconductors Digital video encoder The internal clock can be switched completely to the pixel clock input. In this event, the input FIFO is useless and will be bypassed. The entire pixel clock generation can be locked to the vertical ...
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Philips Semiconductors Digital video encoder Data LOW at the output of the DACs corresponds to 0 IRE, data HIGH at the output of the DACs corresponds to approximately 50 IRE also possible to encode Closed Caption data for ...
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Philips Semiconductors Digital video encoder The input line length can be programmed. The field length is always derived from the field length of the encoder and the pixel clock frequency that is being used. CBO acts as a data request ...
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Acrobat reader. white to force landscape pages to be ... handbook, full pagewidth 4-bit line type index line type pointer 8 2-bit value VALUE ...
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Philips Semiconductors Digital video encoder To ease the trigger set-up for the sync generation module, a set of registers is provided to set up the screen raster which is defined as width and height. A trigger position can be specified ...
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Philips Semiconductors Digital video encoder SEQUENCE use pattern entries and 2 in this sequence (for sync-black-sync-black-null use pattern entries 4 and 5 in this sequence (for sync-black) Write to ...
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Philips Semiconductors Digital video encoder The following Sections give the set of equations required to program the IC for the most common application: A post processor in master mode with non-interlaced video input data. Some variables are defined below: InPix: ...
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Philips Semiconductors Digital video encoder 7.20.4 V ERTICAL SCALER The input vertical offset can be taken from the assumption that the scaler should just have finished writing the first line when the encoder starts reading it: FAL 1716 TXclk YOFS ...
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Philips Semiconductors Digital video encoder Table 8 Usage of bits SLOT and EDGE DATA SLOT CONTROL (EXAMPLE FOR FORMAT 0) SLOT EDGE 1st DATA rising edge G3/ falling edge G3/ rising ...
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Philips Semiconductors Digital video encoder Table 13 Pin assignment for input format 8-BIT INTERLACED C (ITU-R BT.656, 27 MHz CLOCK) RISING RISING CLOCK CLOCK PIN EDGE EDGE ...
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Acrobat reader. white to force landscape pages to be ... 7.22 Bit allocation map Table 16 Slave receiver (slave address 88H) SUB REGISTER FUNCTION ...
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Acrobat reader. white to force landscape pages to be ... SUB REGISTER FUNCTION ADDR. (HEX) Gain U 5B GAINU7 Gain V 5C GAINV7 Gain ...
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Acrobat reader. white to force landscape pages to be ... SUB REGISTER FUNCTION ADDR. (HEX) TTX even request vertical end 79 TTXEVE7 First active ...
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Acrobat reader. white to force landscape pages to be ... SUB REGISTER FUNCTION ADDR. (HEX) Blank enable for NI-bypass, A1 BLEN vertical line skip ...
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Acrobat reader. white to force landscape pages to be ... SUB REGISTER FUNCTION ADDR. (HEX) Input path control FD LUTOFF Cursor bit map FE ...
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Philips Semiconductors Digital video encoder 2 7.23 I C-bus format 2 Table 17 I C-bus write access to control registers; see Table Table 18 I C-bus write access ...
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Philips Semiconductors Digital video encoder 7.24 Slave receiver Table 24 Subaddress 16H DATA BYTE DACF output level adjustment fi steps for all DACs; default after reset is 00H; see Table 25 Table 25 Fine adjustment of DAC output ...
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Philips Semiconductors Digital video encoder Table 28 Subaddress 1BH LOGIC DATA BYTE LEVEL MSM 0 monitor sense mode off; RCOMP, GCOMP and BCOMP bits are not valid; default after reset 1 monitor sense mode on MSA 0 automatic monitor sense ...
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Philips Semiconductors Digital video encoder Table 31 Subaddress 29H LOGIC DATA BYTE LEVEL SRES 0 pin TTX_SRES accepts a teletext bit stream (TTX) 1 pin TTX_SRES accepts a sync reset input (SRES) BE ending point of burst in clock cycles ...
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Philips Semiconductors Digital video encoder Table 34 Subaddress 37H LOGIC DATA BYTE LEVEL YUPSC 0 normal operation of the vertical scaler; default after reset 1 vertical upscaling is enabled YFIL controls the vertical interpolation filter, see Table 35; the filter ...
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Philips Semiconductors Digital video encoder Table 37 Subaddress 3AH LOGIC DATA BYTE LEVEL CBENB 0 data from input ports is encoded 1 colour bar with fixed colours is encoded SYNTV 0 in slave mode, the encoder is only synchronized at ...
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Philips Semiconductors Digital video encoder Table 40 Subaddress 5AH; note 1 DATA BYTE DESCRIPTION CHPS phase of encoded colour subcarrier (including burst) relative to horizontal sync; can be adjusted in steps of 360/256 degrees Note 1. The default after reset ...
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Philips Semiconductors Digital video encoder Table 44 Subaddress 5EH DATA BYTE DESCRIPTION BLNNL variable blanking level Notes 1. Output black level/IRE = BLNNL 2. Output black level/IRE = BLNNL Table 45 Subaddress 5FH DATA BYTE CCRS select cross-colour reduction filter ...
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Philips Semiconductors Digital video encoder Table 47 Subaddress 61H LOGIC DATA BYTE LEVEL DOWND 0 digital core in normal operational mode; default after reset 1 digital core in sleep mode and is reactivated with an I DOWNA 0 DACs in ...
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Philips Semiconductors Digital video encoder Table 49 Subaddresses 63H to 66H (four bytes to program subcarrier frequency) DATA BYTE DESCRIPTION FSC0 to FSC3 f = subcarrier frequency (in multiples fsc of line frequency); f (in multiples of line frequency) Note ...
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Philips Semiconductors Digital video encoder Table 54 Logic levels and function of PHRES DATA BYTE PHRES1 PHRES0 subcarrier reset 0 1 subcarrier reset every two lines 1 0 subcarrier reset every eight fields 1 1 subcarrier reset ...
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Philips Semiconductors Digital video encoder Table 59 Subaddresses 70H to 72H DATA BYTE ADWHS active display window horizontal start; defines the start of the active TV display portion after the border colour values above 1715 (FISE = 1) or 1727 ...
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Philips Semiconductors Digital video encoder Table 64 Subaddresses 78H, 79H and 7CH DATA BYTE TTXEVS first line of occurrence of signal TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0) in even field line = (TTXEVS + 4) for M-systems line = ...
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Philips Semiconductors Digital video encoder Table 69 Subaddress 84H LOGIC DATA BYTE LEVEL DCLK set to logic 1 (default after reset is logic 0) PCLSY 0 pixel clock generator runs free; default after reset 1 pixel clock generator gets synchronized ...
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Philips Semiconductors Digital video encoder Table 74 Subaddresses 91H and 94H DATA BYTE XPIX pixel in X direction; defines half the number of active pixels per input line (identical to the length of CBO pulses) Table 75 Subaddresses 92H and ...
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Philips Semiconductors Digital video encoder Table 79 Subaddress 97H LOGIC DATA BYTE LEVEL HFS 0 horizontal sync is directly derived from input signal (slave mode) at pin HSVGC 1 horizontal sync is derived from a frame sync signal (slave mode) ...
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Philips Semiconductors Digital video encoder Table 82 Subaddresses 9AH and 9CH DATA BYTE XINC incremental fraction of the horizontal scaling engine; Table 83 Subaddresses 9BH and 9CH DATA BYTE YINC incremental fraction of the vertical scaling engine; Table 84 Subaddresses ...
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Philips Semiconductors Digital video encoder Table 89 Subaddress D0H DATA BYTE HLCA RAM start address for the HD sync line count array; the byte following subaddress D0 points to the first cell to be loaded with the next transmitted byte; ...
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Philips Semiconductors Digital video encoder Table 94 Layout of the data bytes in the line pattern array BYTE 0 HPD07 HPD06 1 HPV03 HPV02 2 HPD17 HPD16 3 HPV13 HPV12 4 HPD27 HPD26 5 HPV23 HPV22 6 HPD37 HPD36 7 ...
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Philips Semiconductors Digital video encoder Table 100 Subaddresses DAH and DBH DATA BYTE HTY vertical trigger phase for the HD sync engine in input lines Table 101 Subaddress DCH LOGIC DATA BYTE LEVEL HDSYE 0 the HD sync engine is ...
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Philips Semiconductors Digital video encoder Table 107 Subaddresses FBH and FCH DATA BYTE YCP vertical cursor position Table 108 Subaddress FCH DATA BYTE YHS vertical hot spot of cursor Table 109 Subaddress FDH LOGIC DATA BYTE LEVEL LUTOFF 0 colour ...
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Philips Semiconductors Digital video encoder 7.25 Slave transmitter Table 112 Slave transmitter (slave address 89H) REGISTER SUBADDRESS FUNCTION Status byte 00H Chip ID 1CH FIFO status 80H Table 113 Subaddress 00H LOGIC DATA BYTE LEVEL VER version identification of the ...
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Philips Semiconductors Digital video encoder handbook, full pagewidth (dB ( (1) SCBW = 1. (2) SCBW = 0. handbook, halfpage (1) SCBW = 1. (2) ...
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Philips Semiconductors Digital video encoder handbook, full pagewidth (dB (1) CCRS1 = 0; CCRS0 = 1. (2) CCRS1 = 1; CCRS0 = 0. (3) CCRS1 ...
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Philips Semiconductors Digital video encoder handbook, full pagewidth (dB Fig.8 Luminance transfer characteristic in RGB (excluding scaler). handbook, full pagewidth (dB) 0 ...
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Philips Semiconductors Digital video encoder 8 BOUNDARY SCAN TEST The SAA7104E; SAA7105E has built-in logic and 5 dedicated pins to support boundary scan testing which allows board testing without special hardware (nails). The SAA7104E; SAA7105E follows the “IEEE Std. 1149.1 ...
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Philips Semiconductors Digital video encoder MSB handbook, full pagewidth 31 TDI 0101 4-bit version code MSB handbook, full pagewidth 31 TDI 0101 4-bit version code 9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); all ground ...
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Philips Semiconductors Digital video encoder 10 THERMAL CHARACTERISTICS SYMBOL PARAMETER R thermal resistance from junction to ambient th(j-a) Note 1. The overall R value can vary depending on the board layout. To minimize the effective R th(j-a) ground pins must ...
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Philips Semiconductors Digital video encoder SYMBOL PARAMETER Outputs V LOW-level output voltage OL V HIGH-level output voltage C-bus; pins SDA and SCL V LOW-level input voltage IL V HIGH-level input voltage IH I input current i V ...
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Philips Semiconductors Digital video encoder SYMBOL PARAMETER C RYSTAL SPECIFICATION T ambient temperature amb C load capacitance L R series resistance S C motional capacitance (typical parallel capacitance (typical) 0 Data and reference signal output timing C output ...
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Philips Semiconductors Digital video encoder Notes 2 1. Minimum value for I C-bus bit DOWNA = Minimum value for I C-bus bit DOWND = 1. 3. Levels refer to pins PD11 to PD0, FSVGC, PIXCLKI, VSVGC, PIXCLKO, ...
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Philips Semiconductors Digital video encoder handbook, full pagewidth HSVGC CBO PD handbook, full pagewidth HSVGC VSVGC CBO 2004 Mar 04 XOFS IDEL XPIX HLEN Fig.12 Horizontal input timing. YOFS YPIX Fig.13 Vertical input timing. 59 Product specification SAA7104E; SAA7105E MHB905 ...
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Philips Semiconductors Digital video encoder 11.1 Teletext timing Time t is the time needed to interpolate input data TTX FD and insert it into the CVBS and VBS output signal, such that it appears 9.78 s (PAL) ...
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Philips Semiconductors Digital video encoder 12 APPLICATION INFORMATION DVO 3.3 V digital handbook, full pagewidth supply supply 0.1 F 0.1 F DGND use one capacitor for each V DDD V DDD1 V DDD2 to V DDD4 digital inputs and outputs ...
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Philips Semiconductors Digital video encoder handbook, halfpage 2004 Mar 04 C16 120 pF L2 2.7 H C10 C13 390 pF 560 pF AGND JP11 JP12 FIN FILTER 1 = byp. ll act. Fig.16 FLTR0, FLTR1 and FLTR2 of Fig.15. 62 ...
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Philips Semiconductors Digital video encoder handbook, full pagewidth A5 XTALI 4 (1a) With 3rd-harmonic quartz. Crystal load = 8 pF. handbook, full pagewidth A5 XTALI 27.00 MHz (2a) With direct clock. 2004 Mar 04 SAA7104E SAA7105E A6 ...
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Philips Semiconductors Digital video encoder 12.1 Reconstruction filter Figure 16 shows a possible reconstruction filter for the digital-to-analog converters. Due to its cut-off frequency of 6 MHz not suitable for HDTV applications. 12.2 Analog output voltages The analog ...
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Philips Semiconductors Digital video encoder 13 PACKAGE OUTLINE BGA156: plastic ball grid array package; 156 balls; body 1.15 mm ball A1 index area ...
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Philips Semiconductors Digital video encoder 14 SOLDERING 14.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; ...
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Philips Semiconductors Digital video encoder 14.5 Suitability of surface mount IC packages for wave and reflow soldering methods PACKAGE (3) BGA, HTSSON..T , LBGA, LFBGA, SQFP, SSOP..T USON, VFBGA DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, ...
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Philips Semiconductors Digital video encoder 15 DATA SHEET STATUS DATA SHEET PRODUCT LEVEL (1) STATUS STATUS I Objective data Development II Preliminary data Qualification III Product data Production Notes 1. Please consult the most recently issued data sheet before initiating ...
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Philips Semiconductors Digital video encoder 2 18 PURCHASE OF PHILIPS I Purchase of Philips I components in the I Philips. This specification can be ordered using the code 9398 393 40011. 2004 Mar 04 C COMPONENTS 2 C components conveys ...
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Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. © Koninklijke Philips Electronics N.V. 2004 All rights are reserved. Reproduction in whole or in part is prohibited ...