SAA7105E/V1/G-T NXP Semiconductors, SAA7105E/V1/G-T Datasheet - Page 21
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SAA7105E/V1/G-T
Manufacturer Part Number
SAA7105E/V1/G-T
Description
Video ICs PC-DENC
Manufacturer
NXP Semiconductors
Datasheet
1.SAA7105EV1G-T.pdf
(70 pages)
Specifications of SAA7105E/V1/G-T
Adc/dac Resolution
10b
Screening Level
Commercial
Package Type
LBGA
Pin Count
156
Lead Free Status / RoHS Status
Compliant
Other names
SAA7105E/V1/G,518
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Philips Semiconductors
Table 8 Usage of bits SLOT and EDGE
Table 9 Pin assignment for input format 0
2004 Mar 04
PD11
PD10
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
SLOT EDGE
Digital video encoder
0
0
1
1
8 + 8 + 8-BIT 4 : 4 : 4 NON-INTERLACED
PIN
0
1
0
1
(EXAMPLE FOR FORMAT 0)
DATA SLOT CONTROL
at rising edge
G3/Y3
at falling edge
G3/Y3
at rising edge
R7/C
at falling edge
R7/C
CLOCK EDGE
1st DATA
RGB/C
R
R
7
7
FALLING
B7/C
B6/C
B5/C
B4/C
B3/C
B2/C
B1/C
B0/C
G3/Y3
G2/Y2
G1/Y1
G0/Y0
B
-Y-C
B
B
B
B
B
B
B
B
7
6
5
4
3
2
1
0
R
at falling edge
R7/C
at rising edge
R7/C
at falling edge
G3/Y3
at rising edge
G3/Y3
CLOCK EDGE
2nd DATA
R
R
7
7
RISING
R7/C
R6/C
R5/C
R4/C
R3/C
R2/C
R1/C
R0/C
G7/Y7
G6/Y6
G5/Y5
G4/Y4
R
R
R
R
R
R
R
R
7
6
5
4
3
2
1
0
21
Table 10 Pin assignment for input format 1
Table 11 Pin assignment for input format 2
Table 12 Pin assignment for input format 3
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
8 + 8 + 8-BIT 4 : 2 : 2 NON-INTERLACED C
PIN
5 + 5 + 5-BIT 4 : 4 : 4 NON-INTERLACED RGB
5 + 6 + 5-BIT 4 : 4 : 4 NON-INTERLACED RGB
PIN
PIN
FALLING
CLOCK
C
C
C
C
C
C
C
C
EDGE
B
B
B
B
B
B
B
B
n
7(0)
6(0)
5(0)
4(0)
3(0)
2(0)
1(0)
0(0)
SAA7104E; SAA7105E
CLOCK EDGE
CLOCK EDGE
FALLING
FALLING
CLOCK
RISING
EDGE
Y7(0)
Y6(0)
Y5(0)
Y4(0)
Y3(0)
Y2(0)
Y1(0)
Y0(0)
G2
G1
G0
G2
G1
G0
B4
B3
B2
B1
B0
B4
B3
B2
B1
B0
n
FALLING
CLOCK
Product specification
C
C
C
C
C
C
C
C
EDGE
n + 1
R
R
R
R
R
R
R
R
7(0)
6(0)
5(0)
4(0)
3(0)
2(0)
1(0)
0(0)
CLOCK EDGE
CLOCK EDGE
RISING
RISING
R4
R3
R2
R1
R0
G4
G3
R4
R3
R2
R1
R0
G5
G4
G3
X
B
CLOCK
RISING
EDGE
-Y-C
Y7(1)
Y6(1)
Y5(1)
Y4(1)
Y3(1)
Y2(1)
Y1(1)
Y0(1)
n + 1
R
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