ADV7314KST Analog Devices Inc, ADV7314KST Datasheet
ADV7314KST
Specifications of ADV7314KST
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ADV7314KST Summary of contents
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FEATURES High Definition Input Formats 8-/10-,16-/20-, 24-/30-Bit (4:2:2, 4:4:4) Parallel YCrCb Compliant with: SMPTE 293M (525p) BTA T-1004 EDTV2 525p ITU-R BT.1358 (625p/525p) ITU-R BT.1362 (625p/525p) SMPTE 274M (1080i and 25 Hz SMPTE 296M (720p) RGB in ...
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ADV7314 DETAILED FEATURES High Definition Programmable Features (720p/1080i) 2 Oversampling (148.5 MHz) Internal Test Pattern Generator (Color Hatch, Black Bar, Flat Field/Frame) Fully Programmable YCrCb to RGB Matrix Gamma Correction Programmable Adaptive Filter Control Programmable Sharpness Filter Control CGMS-A (720p/1080i) ...
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TABLE OF CONTENTS FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ADV7314–SPECIFICATIONS Parameter 1 STATIC PERFORMANCE Resolution Integral Nonlinearity 2 Differential Nonlinearity , +ve 2 Differential Nonlinearity , –ve DIGITAL OUTPUTS Output Low Voltage Output High Voltage Three-State Leakage Current Three-State Output Capacitance DIGITAL AND CONTROL INPUTS ...
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DYNAMIC SPECIFICATIONS Parameter PROGRESSIVE SCAN MODE Luma Bandwidth Chroma Bandwidth SNR SNR HDTV MODE Luma Bandwidth Chroma Bandwidth STANDARD DEFINITION MODE Hue Accuracy Color Saturation Accuracy Chroma Nonlinear Gain Chroma Nonlinear Phase Chroma/Luma Intermodulation Chroma/Luma Gain Inequality Chroma/Luma Delay Inequality ...
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ADV7314 TIMING SPECIFICATIONS Parameter 1 MPU PORT SCLOCK Frequency SCLOCK High Pulsewidth SCLOCK Low Pulsewidth Hold Time (Start Condition Setup Time (Start Condition Data Setup Time SDATA, SCLOCK Rise Time, ...
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CLKIN_A P_HSYNC, CONTROL P_VSYNC, INPUTS P_BLANK Y9–Y0 C9–C0 CONTROL OUTPUTS t = CLOCK HIGH TIME CLOCK LOW TIME DATA SETUP TIME DATA HOLD TIME 12 Figure 1. HD Only 4:2:2 Input ...
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ADV7314 CLKIN_A P_HSYNC, CONTROL P_VSYNC, INPUTS P_BLANK Y9–Y0 C9–C0 S9–S0 CONTROL OUTPUTS t = CLOCK HIGH TIME CLOCK LOW TIME DATA SETUP TIME DATA HOLD TIME 12 Figure 3. HD RGB ...
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CLKIN_A P_HSYNC, CONTROL P_VSYNC, INPUTS P_BLANK Y9–Y0 CONTROL OUTPUTS t = CLOCK HIGH TIME CLOCK LOW TIME DATA SETUP TIME DATA HOLD TIME 12 Figure 5. PS 4:2:2 1 10-Bit Interleaved ...
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ADV7314 CLKIN_B P_HSYNC, CONTROL P_VSYNC, INPUTS P_BLANK Y9–Y0 Y0 C9–C0 Cb0 CLKIN_A t S_HSYNC, CONTROL S_VSYNC, INPUTS S_BLANK S9–S0 Cb0 Figure 8. HD 4:2:2 and SD (10-Bit) Simultaneous Input Mode [Input Mode 101]; SD Oversampled [Input Mode 110] HD Oversampled ...
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CLKIN_B P_HSYNC, CONTROL P_VSYNC, INPUTS P_BLANK Cb0 Y9– CLKIN_A t 9 S_HSYNC, CONTROL S_VSYNC, INPUTS S_BLANK S9–S0 Cb0 Figure 10. PS (10-Bit) and SD (10-Bit) Simultaneous Input Mode [Input Mode 100] CLKIN_A t 9 S_HSYNC, CONTROL ...
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ADV7314 CLKIN_A t 9 S_HSYNC, CONTROL S_VSYNC, INPUTS S_BLANK S9–S0/Y9–Y0* Y0 C9–C0 Cb0 CONTROL OUTPUTS *SELECTED BY ADDRESS 0x01 BIT 7 Figure 12. 20-/16-Bit SD Only Pixel Input Mode [Input Mode 000] P_HSYNC P_VSYNC P_BLANK Y9–Y0 C9– ...
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P_HSYNC P_VSYNC P_BLANK Y9– CLK CYCLES FOR 525p CLK CYCLES FOR 625p AS RECOMMENDED BY STANDARD b(MIN) = 244 CLK CYCLES FOR 525p b(MIN) = 264 CLK CYCLES FOR 625p Figure 14. PS 4:2:2 ...
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... This means that the electroplated Sn coating can be soldered with Sn/Pb solder pastes at conventional reflow tem- peratures of 220∞C to 235∞C. Model Package Description ADV7314KST Plastic Quad Flatpack (LQFP) *Analog output short circuit to any power supply or common can indefi- nite duration. ...
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V DD_IO DGND Pin No. Mnemonic Input/Output 11, 57 DGND G 40 AGND G 32 CLKIN_A I 63 CLKIN_B I 36, 45 COMP2, COMP1 O 44 DAC DAC DAC DAC D ...
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ADV7314 Pin No. Mnemonic Input/Output S_HSYNC 50 I/O S_VSYNC 49 I/O 2–9, 12–13 Y9–Y0 I 14–18, 26–30 C9–C0 I 51–55, 58–62 S9–S0 I RESET SET2 SET1 22 SCLK I 21 SDA I/O ...
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MPU PORT DESCRIPTION The ADV7314 supports a 2-wire serial (I processor bus driving multiple peripherals. Two inputs, serial data (SDA) and serial clock (SCL), carry information between any device connected to the bus. Each slave device is recognized by a ...
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ADV7314 Before writing to the subcarrier frequency registers, the ADV7314 must have been reset at least once since power-up. The four subcarrier frequency registers must be updated start- ing with subcarrier frequency register 0 through subcarrier frequency register 3. The ...
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SR7- SR0 Register Bit Description 00h Power Sleep Mode. With this control enabled, the current Mode consumption is reduced to A level. All DACs and Register the internal PLL cct are disabled read from and written to in ...
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ADV7314 SR7- SR0 Register Bit Description 02h Mode Register 0 Reserved Test Pattern Black Bar RGB Matrix 1 Sync on RGB RGB/YUV Output SD Sync HD Sync 03h RGB Matrix 0 04h RGB Matrix 1 05h RGB Matrix 2 06h ...
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SR7- SR0 Register Bit Description 10h HD Mode HD Output Standard Register 1 HD Input Control Signals HD 625p HD 720p HD BLANK Polarity HD Macrovision for 525p/625p 11h HD Mode HD Pixel Data Valid Register 2 HD Test Pattern ...
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ADV7314 SR7- SR0 Register Bit Description Bit 7 12h HD Mode HD Y Delay with Register 3 Respect to Falling Edge of HSYNC HD with Respect to Falling Edge of HSYNC HD CGMS HD CGMS CRC 0 1 13h HD ...
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SR7- SR0 Register Bit Description Level Level Level Reserved 1Ah Reserved 1Bh Reserved 1Ch Reserved 1Dh Reserved 1 E ...
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ADV7314 SR7–SR0 Register Bit Description 38h HD Adaptive Filter HD Adaptive Filter Gain 1 Value A Gain 1 HD Adaptive Filter Gain 1 Value B 39h HD Adaptive Filter HD Adaptive Filter Gain 2 Gain 2 Value A HD Adaptive ...
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SR7– SR0 Register Bit Description 3Eh Reserved 3Fh Reserved 40h SD Mode Register 0 SD Standard SD Luma Filter SD Chroma Filter 41h Reserved 42h SD Mode Register SSAF SD DAC Output 1 SD DAC Output 2 ...
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ADV7314 SR7– SR0 Register Bit Description Mode Register SD VSYNC–3H SD RTC/TR/SCR* SD Active Video Length SD Chroma SD Burst SD Color Bars SD DAC Swap Reserved Reserved 4 7 ...
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SR7- SR0 Register Bit Description 4Ah SD Timing Register 0 SD Slave/Master Mode SD Timing Mode SD BLANK Input SD Luma Delay SD Min. Luma Value SD Timing Reset SD HSYNC Width 4Bh SD Timing Register 1 SD HSYNC to ...
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ADV7314 SR7– SR0 Register Bit Description CGMS/WSS 0 SD CGMS Data SD CGMS CRC SD CGMS on Odd SD CGMS on Even SD WSS 5Ah SD CGMS/WSS 1 SD CGMS/WSS Data 5Bh SD CGMS/WSS 2 SD ...
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SR7- SR0 Register Bit Description DNR 2 DNR Input Select DNR Mode DNR Block Offset Gamma A SD Gamma Curve A Data Points Gamma A SD Gamma Curve ...
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ADV7314 SR7- SR0 Register Bit Description 7Dh Reserved Reserved Reserved Macrovision MV Control Bits Macrovision MV Control Bits Macrovision MV Control Bits ...
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INPUT CONFIGURATION When 10-bit input data is applied, the following bits must be set to 1: Address 0x7C, Bit 1 (Global 10-Bit Enable) Address 0x13, Bit 2 (HD 10-Bit Enable) Address 0x48, Bit 4 (SD 10-Bit Enable) Note that the ...
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ADV7314 Simultaneous Standard Definition and Progressive Scan or HDTV Address [01h]: Input Mode 011(SD 40-Bit, PS 20-Bit) or 101 (SH and HD, SD Oversampled), 110 (SD and HD, HD Oversampled) YCrCb PS, HDTV, or any other HD data must be ...
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Table I provides an overview of all possible input configurations. Input Format ITU-R BT.656 PS Only HDTV Only HD RGB ITU-R BT.656 and PS ITU-R BT.656 and PS ITU-R BT.656 and PS or HDTV ITU-R BT.656 and PS or HDTV ...
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ADV7314 OUTPUT CONFIGURATION These tables show which output signals are assigned to the DACs when the control bits are set accordingly. RGB/YUV Output 02h, Bit RGB HD Input ...
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TIMING MODES HD Async Timing Mode [Subaddress 10h, Bit 3,2] For any input data that does not conform to the standards selectable in input mode, Subaddress 01h, asynchronous tim- ing mode can be used to interface to the ADV7314. Timing ...
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ADV7314 P_HSYNC P_VSYNC P_BLANK* 1 -> -> -> -> -> 0 *When ...
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SD Real-Time Control, Subcarrier Reset, and Timing Reset [Subaddress 44h, Bit 2,1] Together with the RTC_SCR_TR pin and SD Mode Register 3, the ADV7314 can be used in timing reset mode, subcarrier phase reset mode, or RTC mode. Timing Reset ...
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ADV7314 Reset Sequence A reset is activated with a high-to-low transition on the RESET pin [Pin 33] according to the timing specifications. The ADV7314 will revert to the default output configuration. Figure 32 illus- trates the RESET sequence timing. SD ...
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Vertical Blanking Interval The ADV7314 accepts input data that contains VBI data [e.g., CGMS, WSS, VITS and HD modes. For SMPTE 293M [525p] standards, VBI data can be inserted on Lines each frame, or ...
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ADV7314 FILTER SECTION Table VI shows an overview of the programmable filters avail- able on the ADV7314. Table VI. Selectable Filters of the ADV7314 Filter SD Luma LPF NTSC SD Luma LPF PAL SD Luma Notch NTSC SD Luma Notch ...
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SD Internal Filter Response [Subaddress 40h; Subaddress 42, Bit 0] The Y filter supports several different frequency responses includ- ing two low-pass responses, two notch responses, an extended (SSAF) response, with or without gain boost/attenuation, a CIF response and a ...
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ADV7314–Typical Performance Characteristics PROG SCAN Pr/Pb RESPONSE. LINEAR INTERP FROM 4:2:2 TO 4:4:4 0 –10 –20 –30 –40 –50 –60 –70 – 100 120 FREQUENCY (MHz) TPC 1. PS – Oversampling Filter—Linear Y ...
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FREQUENCY (MHz) TPC 7. Luma NTSC Low-Pass Filter 0 –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) TPC 8. Luma NTSC Notch Filter ...
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ADV7314 –2 –4 –6 –8 –10 – FREQUENCY (MHz) TPC 13. Luma SSAF Filter—Programmable Responses 1 0 –1 –2 –3 –4 – FREQUENCY (MHz) TPC 14. Luma ...
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FREQUENCY (MHz) TPC 19. Chroma 2.0 MHz LP Filter 0 –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) TPC 20. Chroma 1.0 MHz ...
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ADV7314 COLOR CONTROLS AND RGB MATRIX HD/PS Y Level, Cr Level, Cb Level [Subaddress 16h–18h] Three 8-bit registers at Address 16h, 17h, 18h are used to program the output color of the internal HD test pattern generator, whether it is ...
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SD Hue Adjust Value [Subaddress 60h] The hue adjust value is used to adjust the hue on the composite and chroma outputs. These eight bits represent the value required to vary the hue of the video data, i.e., the variance ...
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ADV7314 PROGRAMMABLE DAC GAIN CONTROL DACs A, B, and C are controlled by Register 0A. DACs D, E, and F are controlled by Register 0B. 2 The I C control registers will adjust the output signal gain up or down ...
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Gamma Correction [Subaddress 24h–37h for HD, Subaddress 66h–79h for SD] Gamma correction is available for SD and HD video. For each standard there are 20 8-bit registers. They are used to program the gamma correction curves A and B. HD ...
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ADV7314 HD Sharpness Filter Control and Adaptive Filter Control [Subaddress 20h, 38h–3Dh] There are three Filter modes available on the ADV7314: sharpness filter mode and two adaptive filter modes. HD Sharpness Filter Mode To enhance or attenuate the Y signal ...
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HD Sharpness Filter and Adaptive Filter Application Examples HD Sharpness Filter Application The HD sharpness filter can be used to enhance or attenuate the Y video output signal. The following register settings were used to achieve the results shown in ...
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ADV7314 Adaptive Filter Control Application Figures 44 and 45 show a typical signal to be processed by the adaptive filter control block. Figure 44. Input Signal to Adaptive Filter Control Figure 45. Output Signal after Adaptive Filter Control The following ...
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SD DIGITAL NOISE REDUCTION [Subaddress 63h, 64h, 65h] DNR is applied to the Y data only. A filter block selects the high frequency, low amplitude components of the incoming signal [DNR input select]. The absolute value of the filter output ...
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ADV7314 Block Size Control [Address 64h, Bit 7] This bit is used to select the size of the data blocks to be processed. Setting the block size control function to a Logic 1 defines a 16 pixel ¥ 16 pixel ...
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SD ACTIVE VIDEO EDGE [Subaddress 42h, Bit 7] When the active video edge is enabled, the first three pixels and the last three pixels of the active video on the luma channel are scaled in such a way that maximum ...
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ADV7314 BOARD DESIGN AND LAYOUT CONSIDERATIONS DAC Termination and Layout Considerations The ADV7314 contains an on-board voltage reference. The ADV7314 can be used with an external V The R resistors are connected between the R SET AGND and are used ...
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H DAC OUTPUT 3 22pF 300 300 22pF 4 1.8k 600 Figure 56. Example for Output Filter for PS, 8 ¥ Oversampling DAC OUTPUT 3 470nH 220nH 75 1 300 33pF 82pF 4 Figure 57. Example for Output Filter ...
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ADV7314 PC BOARD LAYOUT CONSIDERATIONS The ADV7314 is optimally designed for lowest noise perfor- mance, for both radiated and conducted noise. To complement the excellent noise performance of the ADV7314 impera- tive that great care be given to ...
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ADV7314 0 DD_IO 5k COMP1 V AA 4.7k 4 820pF GND_IO AGND DGND 680 3.9nF UNUSED INPUTS SHOULD BE GROUNDED. REV. 0 POWER SUPPLY DECOUPLING FOR EACH POWER SUPPLY GROUP V 10nF ...
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ADV7314 APPENDIX 1—COPY GENERATION MANAGEMENT SYSTEM PS CGMS Data Registers 2–0 [Subaddress 21h, 22h, 23h] PS CGMS is available in 525p mode conforming to CGMS-A EIA-J CPR1204-1, transfer method of video ID information using vertical blanking interval (525p system), March ...
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IRE +70 IRE 0 IRE –40 IRE 11.2 s +700mV REF 70% 10% 0mV –300mV 4T 3.128 s 90ns +700mV REF 70% 10% 0mV –300mV 4T 4.15 s 60ns ...
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ADV7314 APPENDIX 2—SD WIDE SCREEN SIGNALING [Subaddress 59h, 5Ah, 5Bh] The ADV7314 supports wide screen signaling (WSS) conforming to the standard. WSS data is transmitted on Line 23. WSS data can be transmitted only when the ADV7314 is configured in ...
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APPENDIX 3—SD CLOSED CAPTIONING [Subaddress 51h–54h] The ADV7314 supports closed captioning conforming to the standard television synchronizing waveform for color transmis- sion. Closed captioning is transmitted during the blanked active line time of Line 21 of the odd fields and ...
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ADV7314 APPENDIX 4—TEST PATTERNS The ADV7314 can generate SD and HD test patterns CH2 200mV M 10 30.6000 s Figure 67. NTSC Color Bars T 2 CH2 200mV M 10 30.6000 s Figure 68. ...
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T 2 CH2 200mV M 4 1.82872ms Figure 73. 525p Field Pattern T 2 CH2 200mV M 4 1.84176ms Figure 74. 525p Black Bar (–35 mV, 0 mV, 7 mV, 14 mV, 21 mV, 28 mV, ...
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ADV7314 APPENDIX 5—SD TIMING MODES [Subaddress 4Ah] Mode 0 (CCIR-656)—Slave Option (Timing Register 0 TR0 = The ADV7314 is controlled by the SAV (start active video) and EAV (end active video) time ...
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Mode 0 (CCIR-656)—Master Option (Timing Register 0 TR0 = The ADV7314 generates H, V, and F signals required for the SAV (start active video) and EAV (end active video) time codes in ...
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ADV7314 ANALOG VIDEO Mode 1—Slave Option (Timing Register 0 TR0 = this mode, the ADV7314 accepts horizontal SYNC and odd/even field signals. A transition of the field input ...
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Mode 1—Master Option (Timing Register 0 TR0 = this mode, the ADV7314 can generate horizontal sync and odd/ even field signals. A transition of the field input when HSYNC is low ...
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ADV7314 Mode 2—Slave Option (Timing Register 0 TR0 = this mode, the ADV7314 accepts horizontal and vertical sync signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the ...
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Mode 2—Master Option (Timing Register 0 TR0 = this mode, the ADV7314 can generate horizontal and vertical sync signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the ...
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ADV7314 Mode 3—Master/Slave Option (Timing Register 0 TR0 = this mode, the ADV7314 accepts or generates horizontal sync and odd/even field signals. ...
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APPENDIX 6—HD TIMING FIELD 1 1124 1125 1 P_VSYNC P_HSYNC FIELD 2 561 562 563 P_VSYNC P_HSYNC REV. 0 VERTICAL BLANKING INTERVAL VERTICAL BLANKING INTERVAL 567 568 565 566 564 Figure 90. 1080i HSYNC and ...
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ADV7314 APPENDIX 7—VIDEO OUTPUT LEVELS HD YPrPb Output Levels EIA-770.2, STANDARD FOR Y INPUT CODE 940 64 EIA-770.2, STANDARD FOR Pr/Pb 960 512 64 Figure 91. EIA 770.2 Standard Output Signals (525p/625p) EIA-770.1, STANDARD FOR Y INPUT CODE 940 64 ...
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RGB Output Levels 700mV 550mV 300mV 700mV 300mV 700mV 300mV Figure 95. HD RGB Output Levels 700mV 550mV 300mV 0mV 700mV 300mV 0mV 700mV 300mV 0mV Figure 96. HD RGB Output Levels—RGB Sync Enabled REV. 0 300mV 550mV 300mV 550mV ...
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ADV7314 YPrPb Output Levels 280mV 220mV 160mV 60mV Figure 99. U Levels—NTSC 280mV 220mV 160mV 60mV Figure 100. U Levels—PAL 200mV 1260mV 1000mV 140mV Figure 101. U Levels—NTSC 332mV 110mV 332mV 110mV 2150mV 900mV –76– 2150mV 200mV 1260mV 1000mV 900mV ...
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VOLTS IRE:FLT 100 0 –50 0 APL = 44.5% 525 LINE NTSC SLOW CLAMP TO 0.00V AT 6.72 s VOLTS IRE:FLT 0.4 0.2 0 –0.2 –50 –0.4 0 NOISE REDUCTION: 15.05dB APL NEEDS SYNC-SOURCE! 525 LINE NTSC NO ...
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ADV7314 VOLTS IRE:FLT 0.6 0.4 0.2 0 –0.2 10 NOISE REDUCTION: 15.05dB APL = 44.3% 525 LINE NTSC NO FILTERING SLOW CLAMP TO 0.00 AT 6.72 s VOLTS 0.6 0.4 0.2 0 –0.2 0 NOISE REDUCTION: 0.00dB APL = 39.1% ...
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VOLTS 0.5 0 –0.5 10 APL NEEDS SYNC SOURCE! 625 LINE PAL NO FILTERING SLOW CLAMP TO 0.00 AT 6.72 s VOLTS 0 APL NEEDS SYNC SOURCE! 625 LINE PAL NO FILTERING SLOW CLAMP TO 0.00 AT 6.72 ...
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ADV7314 APPENDIX 8—VIDEO STANDARDS SMPTE 274M ANALOG WAVEFORM 4T EAV CODE INPUT PIXELS CLOCK SAMPLE NUMBER 2112 2116 2156 FVH* = FVH AND PARITY BITS SAV/EAV: LINE 1–562 ...
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ACTIVE VIDEO 522 523 524 525 ACTIVE VIDEO 622 623 624 625 747 748 749 750 FIELD 1 1124 1125 FIELD 2 561 562 REV. 0 VERTICAL BLANK Figure 113. SMPTE 293M ...
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ADV7314 64-Lead Low Profile Quad Flat Package [LQFP 1.40 1.35 0.15 SEATING 0.10 MAX 0.05 PLANE COPLANARITY VIEW A ROTATED 90 CCW OUTLINE DIMENSIONS (ST-64) Dimensions shown in millimeters 0.75 12.00 BSC 1.60 0.60 MAX 0.45 ...
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