ADV7185KSTZ Analog Devices Inc, ADV7185KSTZ Datasheet - Page 18

• Manufacturer Part Number: ADV7185KSTZ
• Manufacturer: Analog Devices Inc

Specifications of ADV7185KSTZ

• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: LQFP
• Pin Count: 80
• Lead Free Status / RoHS Status: Compliant

ADV7185
Manual Clock Control
The ADV7185 offers several output clock mode options: the
output clock frequency can be set by the input video line length, a
fixed 27 MHz output, or by a user-programmable value. Informa-
tion on the clock control register at 28h can be found in the
register access map. When Bit 6 of this register (CLKMANE) is
set to Logic “1,” the output clock frequency will be determined
by the user-programmable value (CLKVAL[15:0]). Using this
mode, the output clock frequency is calculated as:
For example, a required clock frequency of 25 MHz would yield
a CLKVAL of 2D266h (184934).
Color Subcarrier Control
The color subcarrier manual frequency control register
(CSMF[27:0]) can be used to set the DDFS block to a user-
defined frequency. This function can be useful if the color
subcarrier frequency of the incoming video signal is outside
the standard F
Logic “1” enables the manual frequency control, the frequency
of which will be determined by CSMF[27:0]. The value of
CSMF[27:0] can be calculated as:
*Required
MPU PORT DESCRIPTION
The ADV7185 supports a 2-wire serial (I
processor bus driving multiple peripherals. Two inputs, serial
data (SDATA) and serial clock (SCLOCK), carry information
between any device connected to the bus. Each slave device is
recognized by a unique address. The ADV7185 has two possible
slave addresses for both read and write operations. These are
unique addresses for the device and are illustrated in Figure 27.
The LSB sets either a read or write operation. Logic Level “1”
corresponds to a read operation while Logic Level “0” corre-
sponds to a write operation. A1 is set by setting the ALSB pin of
the ADV7185 to Logic Level “0” or Logic Level “1.”
1
LLC
0
=
SC
CSMF
CLKVAL
lock range. Setting Bit 4 reg 23h (CSM) to a
Figure 27. Slave Address
0
[ : ]
27 0
2
20
[ : ]
0
17 0
=
F
SC
×
1
28
*
×
×
27
16
0
2
3
C-compatible) micro-
2
MHz
28
×
SET UP BY
ADDRESS
CONTROL
27
ALSB
A1
MHz
0
1
READ/WRITE
CONTROL
X
WRITE
READ
–18–
To control the device on the bus the following protocol must
be followed. First the master initiates a data transfer by estab-
lishing a start condition, defined by a high to low transition on
SDATA while SCLOCK remains high. This indicates that an
address/data stream will follow. All peripherals respond to the
start condition and shift the next 8 bits (7-Bit Address + R/W
Bit). The bits are transferred from MSB down to LSB. The
peripheral that recognizes the transmitted address responds by
pulling the data line low during the ninth clock pulse. This is
known as an acknowledge bit. All other devices withdraw
from the bus at this point and maintain an idle condition. The
idle condition is where the device monitors the SDATA and
SCLOCK lines waiting for the start condition and the correct
transmitted address. The R/W bit determines the direction of
the data. A Logic “0” on the LSB of the first byte means that
the master will write information to the peripheral. A Logic “1”
on the LSB of the first byte means that the master will read
information from the peripheral.
The ADV7185 acts as a standard slave device on the bus. The
data on the SDATA pin is 8 bits long, supporting the 7-bit
addresses plus the R/W bit. The ADV7185 has 71 subaddresses
to enable access to the internal registers. It therefore interprets
the first byte as the device address and the second byte as the
starting subaddress. The subaddresses autoincrement, allowing
data to be written to or read from the starting subaddress. A
data transfer is always terminated by a stop condition. The user
can also access any unique subaddress register on a one-by-one
basis, without having to update all the registers.
Stop and start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of sequence
with normal read and write operations, they cause an immediate
jump to the idle condition. During a given SCLOCK high
period, the user should only issue one start condition, one stop
condition, or a single stop condition followed by a single start
condition. If an invalid subaddress is issued by the user, the
ADV7185 will not issue an acknowledge and will return to the
idle condition. If the user exceeds the highest subaddress in
autoincrement mode, the following action will be taken:
1. In read mode, the highest subaddress register contents
2. In write mode, the data for the invalid byte will not be loaded
will continue to be output until the master device issues
a no-acknowledge. This indicates the end of a read. A
no-acknowledge condition is where the SDATA line is
not pulled low on the ninth pulse.
into any subaddress register, a no-acknowledge will be issued
by the ADV7185, and the part will return to the idle condition.
REV. 0