ADV7176AKS Analog Devices Inc, ADV7176AKS Datasheet - Page 22

• Manufacturer Part Number: ADV7176AKS
• Manufacturer: Analog Devices Inc

Specifications of ADV7176AKS

• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: MQFP
• Pin Count: 44
• Lead Free Status / RoHS Status: Not Compliant

ADV7175A/ADV7176A
also access any unique subaddress register on a one by one basis
without having to update all the registers. There is one excep-
tion. The subcarrier frequency registers should be updated in
sequence, starting with Subcarrier Frequency Register 0. The
auto increment function should then be used to increment and
access Subcarrier Frequency Registers 1, 2 and 3. The subcarrier
frequency registers should not be accessed independently.
Stop and start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of sequence
with normal read and write operations, they cause an immediate
jump to the idle condition. During a given SCLOCK high
period, the user should issue only one start condition, one
stop condition or a single stop condition followed by a single
start condition. If an invalid subaddress is issued by the user,
the ADV7175A/ADV7176A will not issue an acknowledge and
will return to the idle condition. If, in auto-increment mode
the user exceeds the highest subaddress, the following action
will be taken:
*TTX REGISTERS ARE AVAILABLE IN PAL MODE ONLY
SR5 SR4 SR3 SR2 SR1 SR0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
IN NTSC MODE THESE REGISTERS CONTROL PEDESTAL
•
•
SR7
ZERO SHOULD BE WRITTEN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
•
•
0
0
TO THESE BITS
SR7–SR6 (00)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
•
•
0
0
SR6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
•
•
0
1
SEQUENCE
SEQUENCE
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
•
•
1
0
WRITE
READ
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
•
•
1
0
SR5
ADV7175A SUBADDRESS REGISTER
MODE REGISTER 0
MODE REGISTER 1
SUB CARRIER FREQ REGISTER 0
SUB CARRIER FREQ REGISTER 1
SUB CARRIER FREQ REGISTER 2
SUB CARRIER FREQ REGISTER 3
SUB CARRIER PHASE REGISTER
TIMING REGISTER 0
CLOSED CAPTIONING EXTENDED DATA
CLOSED CAPTIONING EXTENDED DATA
CLOSED CAPTIONING DATA
CLOSED CAPTIONING DATA
TIMING REGISTER 1
MODE REGISTER 2
NTSC PEDESTAL CONTROL REG 0 (FIELD 1/3)/TTX SETUP REG 0*
NTSC PEDESTAL CONTROL REG 1 (FIELD 1/3)/TTX SETUP REG 1*
NTSC PEDESTAL CONTROL REG 2 (FIELD 2/4)/TTX SETUP REG 2*
NTSC PEDESTAL CONTROL REG 3 (FIELD 2/4)/TTX SETUP REG 3*
MODE REGISTER 3
MACROVISION REGISTER
MACROVISION REGISTER
TTXREQ CONTROL REGISTER
S
S
S = START BIT
P = STOP BIT
SLAVE ADDR A(S)
SLAVE ADDR A(S)
"
"
SR4
"
"
LSB = 0
SR3
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
BYTE 0
BYTE 1
SUB ADDR
SUB ADDR
SR2
BYTE 0
BYTE 1
A(S)
A(S) S SLAVE ADDR A(S)
SR1
DATA
SR0
LSB = 1
*TTX REGISTERS ARE AVAILABLE IN PAL MODE ONLY
1. In Read Mode, the highest subaddress register contents
2. In Write Mode, the data for the invalid byte will not be
Figure 29 illustrates an example of data transfer for a read
sequence and the start and stop conditions.
Figure 30 shows bus write and read sequences.
SR5 SR4 SR3 SR2 SR1 SR0
SCLOCK
IN NTSC MODE THESE REGISTERS CONTROL PEDESTAL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
A(S)
SDATA
A(S) = NO-ACKNOWLEDGE BY SLAVE
A(M) = NO-ACKNOWLEDGE BY MASTER
will continue to be output until the master device issues a
no-acknowledge. This indicates the end of a read. A no-
acknowledge condition is where the SDATA line is not pulled
low on the ninth pulse.
loaded into any subaddress register, a no-acknowledge will
be issued by the ADV7175A/ADV7176A and the part will
return to the idle condition.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
START ADDR R/W ACK SUBADDRESS ACK
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
S
DATA
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1-7
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
DATA
8
A(M)
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
ADV7176A SUBADDRESS REGISTER
MODE REGISTER 0
MODE REGISTER 1
SUB CARRIER FREQ REGISTER 0
SUB CARRIER FREQ REGISTER 1
SUB CARRIER FREQ REGISTER 2
SUB CARRIER FREQ REGISTER 3
SUB CARRIER PHASE REGISTER
TIMING REGISTER 0
CLOSED CAPTIONING EXTENDED DATA
CLOSED CAPTIONING EXTENDED DATA
CLOSED CAPTIONING DATA
CLOSED CAPTIONING DATA
TIMING REGISTER 1
MODE REGISTER 2
NTSC PEDESTAL CONTROL REG 0 (FIELD 1/3)/TTX SETUP REG 0*
NTSC PEDESTAL CONTROL REG 1 (FIELD 1/3)/TTX SETUP REG 1*
NTSC PEDESTAL CONTROL REG 2 (FIELD 2/4)/TTX SETUP REG 2*
NTSC PEDESTAL CONTROL REG 3 (FIELD 2/4)/TTX SETUP REG 3*
MODE REGISTER 3
TTXREQ CONTROL REGISTER
9
A(S) P
1-7
DATA
8
9
A(M)
BYTE 0
BYTE 1
1-7
DATA
P
BYTE 0
BYTE 1
8
ACK
9
STOP
P