LTC1264CSW#TRMPBF Linear Technology, LTC1264CSW#TRMPBF Datasheet - Page 3

LTC1264CSW#TRMPBF

Manufacturer Part Number
LTC1264CSW#TRMPBF
Description
Manufacturer
Linear Technology
Datasheet

Specifications of LTC1264CSW#TRMPBF

Architecture
Switched Capacitor
Order Filter (max)
8th
Single Supply Voltage (typ)
5/9/12/15V
Dual Supply Voltage (typ)
±3/±5V
Power Supply Requirement
Single/Dual
Single Supply Voltage (min)
4.75V
Single Supply Voltage (max)
16V
Dual Supply Voltage (min)
±2.375V
Dual Supply Voltage (max)
±8V
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Package Type
SOIC W
Filter Type
Universal
Lead Free Status / RoHS Status
Compliant

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temperature range, otherwise specifications are at T
Q = 5, unless otherwise noted.
PARAMETER
DC Offset Voltage (Note 3)
Clock Feedthrough
Maximum Clock Frequency
Power Supply Current
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: Please refer to Typical Maximum Q vs Clock Frequency graphs.
Note 3: Calculations of output DC offsets of one 2nd order section. Also
see Block Diagram.
TYPICAL PERFOR
ELECTRICAL C
MODE
1b
1
2
3
26
24
22
20
18
16
14
12
10
8
6
4
2
0
1.5
Typical Maximum Q
vs Clock Frequency
B
2.0
V
V
[V
• [R4/(R2 + R4)] + V
V
A
OS1
OS1
OS2
CLOCK FREQUENCY (MHz)
OS1
2.5
[(1Q) + 1 ||H
[(1/Q) + 1 + R2/R1] – V
(1 + R2/R1 + R2/R3 + R2/R4) – V
3.0
PINS 2, 11, 14, 23
3.5
HARA TERISTICS
A. MODES 1, 1b
B. MODES 3, 3a
OLP
V
4.0
OSN
OS2
||] – V
V
T
A
S
W
= ±7.5V
≤ 85°C
[R2/(R2 + R4)]
4.5
OS3
A
C
1264 G01
OS3
U
/Q
5.0
/Q
CE
CONDITIONS
V
V
V
V
V
V
V
V
C
OS3
OS1
OS2
OS3
S
S
S
S
S
HARA TERISTICS
= ±7.5V (f
= ±5V (f
= ±2.375V (f
= ±7.5V, T
= ±5V
26
24
22
20
18
16
14
12
10
(R2/R3)]
8
6
4
2
0
(DC Offset of Input Inverter)
(DC Offset of First Integrator)
(DC Offset of Second Integrator)
1.0
A
Typical Maximum Q
vs Clock Frequency
= 25°C. (Complete Filter) V
B
CLK
1.5
CLK
A
The
is a Square Wave)
C
= 25°C
CLOCK FREQUENCY (MHz)
CLK
is a Square Wave)
A
2.0
PINS 3, 10, 15, 22
is a Square Wave)
denotes the specifications which apply over the full operating
V
2.5
V
V
V
V
Note 4: The center frequency f
OSBP
OS3
OS3
OS3
OS3
f
O
A. MODES 1, 1b
B. MODES 3, 3a
3.0
(measured) – f
V
T
S
A
= ±5V
≤ 85°C
f
3.5
O
S
(ideal)
1264 G02
= ±5V, f
4.0
V
≈(V
V
V
– V
O
OSN
OSN
OS1
(ideal)
OS3
OSN
CLK
[1 + R4/R1 + R4/R2 + R4/R3] – V
– V
– V
(R4/R3)
– V
OS2
OS2
= 1MHz, all sides mode 1, f
• 100
O
OS2
20
18
16
14
12
10
, error is calculated as:
MIN
PINS 4, 9, 16, 21
8
6
4
2
0
9
1.0
)(1 + R5/R6)
Typical Maximum Q
vs Clock Frequency
V
B
OSLP
1.2
CLOCK FREQUENCY (MHz)
TYP
A
160
120
90
14
6
1.4
LTC1264
MAX
±20
±45
±45
1.6
23
26
OS2
V
T
A. MODES 1, 1b
B. MODES 3, 3a
S
A
O
(R4/R2)
≤ 85°C
= SINGLE 5V
= 50kHz,
1.8
µV
µV
µV
UNITS
1264 G03
1264fb
3
MHz
RMS
RMS
RMS
mV
mV
mV
mA
mA
2.0

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