LTC1264CSW#TRMPBF Linear Technology, LTC1264CSW#TRMPBF Datasheet - Page 5

• Manufacturer Part Number: LTC1264CSW#TRMPBF
• Manufacturer: Linear Technology

Specifications of LTC1264CSW#TRMPBF

• Architecture: Switched Capacitor
• Order Filter (max): 8th
• Single Supply Voltage (typ): 5/9/12/15V
• Dual Supply Voltage (typ): ±3/±5V
• Power Supply Requirement: Single/Dual
• Single Supply Voltage (min): 4.75V
• Single Supply Voltage (max): 16V
• Dual Supply Voltage (min): ±2.375V
• Dual Supply Voltage (max): ±8V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Package Type: SOIC W
• Filter Type: Universal
• Lead Free Status / RoHS Status: Compliant

PI FU CTIO S
V
the V
capacitor to an adequate analog ground. The filter’s power
supplies should be isolated from other digital or high
voltage analog supplies. A low noise linear supply is
recommended. Using a switching power supply will lower
the signal-to-noise ratio of the filter. The supply during
power-up should have a slew rate less than 1V/µs. When
V
ground, a diode should clamp V
Figures 1 and 2 show typical connections for dual and
single supply operation.
+
+
, V
U
is applied before V
–
–
GROUND
ANALOG
PLANE
(Pins 7, 19): Power Supply Pins. The V
*
Figure 1. Dual Supply Ground Plane Connections
(Pin 19) should each be bypassed with a 0.1µF
7.5V
OPTIONAL, 1N4148, 1N5819
0.1µF
STAR
SYSTEM
GROUND
U
10
11
12
1
2
3
4
5
6
7
8
9
U
–
LTC1264
and V
GROUND
DIGITAL
PLANE
–
is allowed to go above
24
23
22
21
20
19
18
17
16
15
14
13
–
to prevent latch-up.
SOURCE
CLOCK
–7.5V
200Ω
0.1µF
*
+
(Pin 7) and
1264 F01
AGND (Pin 6): Analog Ground Pin. The filter performance
depends on the quality of the analog signal ground. For
either dual or single supply operation, an analog ground
plane surrounding the package is recommended. The
analog ground plane should be connected to any digital
ground at a single point. For dual supply operation, Pin 6
should be connected to the analog ground plane. For
single supply operation, Pin 6 should be biased at 1/2
supply and should be bypassed to the analog ground plane
with at least a 1µF capacitor (Figure 2). For single 5V
operation and f
biased at 2V. This minimizes passband gain and phase
variations.
*
17, 20 SHOULD BE TIED TO PIN 6
FOR MODE 3, THE S NODE PINS 5, 8,
GROUND
ANALOG
PLANE
1µF
V
STAR
SYSTEM
GROUND
+
Figure 2. Single Supply Ground Plane Connections
+
5k
5k
V
CLK
+
V
/2
+
*
*
10
11
12
greater than 1MHz, pin 6 should be
1
2
3
4
5
6
7
8
9
LTC1264
GROUND
DIGITAL
PLANE
24
23
22
21
20
19
18
17
16
15
14
13
*
*
SOURCE
CLOCK
200Ω
LTC1264
1264 F02
1264fb
5