LM1267NA National Semiconductor, LM1267NA Datasheet - Page 19

• Manufacturer Part Number: LM1267NA
• Manufacturer: National Semiconductor

Specifications of LM1267NA

• Power Supply Requirement: Single
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Mounting: Through Hole
• Pin Count: 24
• Package Type: MDIP
• Lead Free Status / RoHS Status: Not Compliant

DAC Interface Register Definitions
Register name: DAC 3 (06h)
Bits 7–0: DAC 3. These eight bits determine the output
DAC 4 Register (I
Register name: DAC 4 (07h)
Bits 7–0: DAC 4. These eight bits determine the output
DC Offset and OSD Contrast Control Register (I
dress 08h)
Register name: DC Offset/OSD Cont. (08h)
Bits 2–0: DC Offset Control. These three bits determine the
Bits 4–3: OSD Contrast Control. These two bits determine
Bits 7–5: Reserved.
Global Video Control Register (I
Register name: Global Control (09h)
Bit 0:
Bit 1:
Bit 2:
Bit 3:
Bit 7
D3–7 D3–6 D3–5 D3–4 D3–3 D3–2 D3–1 D3–0
Bit 7
D4–7 D4–6 D4–5 D4–4 D4–3 D4–2 D4–1 D4–0
Bit 7
RSV RSV RSV OSDC1 OSDC0 DC2 DC1 DC0
(Continued)
Bit 7
RSV
RSV
voltage of DAC 3.
voltage of DAC 4.
active video DC offset to all three channels.
the contrast level of the OSD information.
Blank Video. When this bit is a one, blank the
video output. When this bit is a zero allow normal
video out.
Power Save. When this bit is a one, shut down
the analog circuits to support sleep mode. When
this bit is a zero enable the analog circuits for
normal operation.
MUST BE SET TO “0” FOR PROPER OPERA-
TION.
DAC1–3 Configuration. When this bit is a zero
the DAC outputs of DAC1–3 are full scale
(0V–4.5V). When this bit is 1, the range of
DAC1–3 are halved (0V–2.25V).
0
2
C address 07h)
DCF4
DCF1–3
2
C address 09h)
0
PS
2
C ad-
Bit 0
Bit 0
Bit 0
Bit 0
BV
19
Bit 4:
Bit 5:
Bits 7–6: Reserved.
Increment Mode Register (I
Register name: Increment Mode (0Ah)
Bit 0:
Bit 1:
Bits 7–2: Reserved.
Clamp Polarity and Bandwidth (I
Register name: Clamp/BW (0Bh)
Bits 2–0: Bandwidth. Used to set the bandwidth of the
Bit 3:
Bits 7–4: Reserved.
Software Reset Register (I
Register name: Software Reset (0Fh)
Bit 0:
Bits 7–1: Reserved.
Bit 7
RSV
Bit 7
RSV
Bit 7
RSV
RSV
RSV
RSV
DAC4 Configuration. When this bit is a zero the
DAC4 output is not mixed with the other DAC
outputs. When the bit is one, 50% of the DAC4
output is added to DAC1–3.
MUST BE SET TO “0” FOR PROPER OPERA-
TION.
Increment Enable. When set to a “0”, the default
value, the increment mode is enabled. This al-
lows the registers to be updated sequentially by
sending another block of data.
MUST BE SET TO “0” FOR PROPER OPERA-
TION.
preamp. The default is 100. When all bits are set
to “1”, the LM1267 will have maximum bandwidth,
when all bits are set to “0” the LM1267 will have
minimum bandwidth.
Determines the polarity of the clamp signal used
by the LM1267, “0” (default) is a positive clamp
signal, “1” is a negative going clamp signal.
Software Reset. Setting this bit causes a software
reset. All registers (except this one) are loaded
with their default values. All operations currently
in progress are aborted (except for I
tions). This bit automatically clears itself when the
reset has been completed.
RSV
RSV
RSV
RSV
RSV
RSV
2
2
C address 0Fh)
CLMP
C address 0Ah)
RSV
RSV
2
C address 0Bh)
RSV
RSV
BW1
RSV
TST
BW2
2
www.national.com
C transac-
SRST
INCR
BW0
Bit 0
Bit 0
Bit 0