AD9923BBCZRL Analog Devices Inc, AD9923BBCZRL Datasheet - Page 73

• Manufacturer Part Number: AD9923BBCZRL
• Manufacturer: Analog Devices Inc

Specifications of AD9923BBCZRL

• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Sample Rate: 36MSPS
• Input Voltage Range: 0.7V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 12b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -25C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 105
• Package Type: CSPBGA
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Compliant

Address
37
38
Table 49. CLPOB and PBLK Masking Registers
Address
40
41
42
43
44
45
Data
Bits
[7:4]
[11:8]
[15:12]
[19:16]
[23:20]
[7:0]
[15:8]
[5:0]
[7:6]
[8]
[10:9]
[11]
Data
Bits
[11:0]
[12]
[24:13]
[11:0]
[12]
[24:13]
[11:0]
[12]
[24:13]
[11:0]
[12]
[24:13
[11:0]
[12]
[24:13]
[11:0]
[12]
[24:13]
Default
Value
1
1
1
1
1
24
0
0
0
0
2
0
Default
Value
FFF
0
FFF
FFF
0
FFF
FFF
0
FFF
FFF
0
FFF
FFF
0
FFF
FFF
0
FFF
Update
VD
VD
VD
VD
VD
VD
Update
Type
SCK
SCK
Name
CLPOBMASKSTART1
Unused
CLPOBMASKEND1
CLPOBMASKSTART2
Unused
CLPOBMASKEND2
CLPOBMASKSTART3
Unused
CLPOBMASKEND3
PBLKMASKSTART1
Unused
PBLKMASKEND1
PBLKMASKSTART12
Unused
PBLKMASKEND2
PBLKMASKSTART3
Unused
PBLKMASKEND3
Name
H2DRV
H3DRV
H4DRV
HLDRV
RGDRV
SHPLOC
SHDLOC
DOUTPHASE
Unused
DCLKMODE
DOUTDELAY
DCLKINV
Rev. 0 | Page 73 of 88
Description
H2 drive strength.
H3 drive strength.
H4 drive strength.
HL drive strength.
RG drive strength.
SHP sample location.
SHD sample location.
DOUT phase control.
Must be set to 0.
DCLK mode. 0: DCLK tracks DOUT phase, 1: DCLK phase is fixed.
Data output delay (t
Invert DCLK output.
0: no delay.
1: ~4 ns.
2: ~8 ns.
3: ~12 ns.
0: no inversion.
1: inversion of DCLK.
Description
CLPOB Masking Start Line 1.
Must be set to 0.
CLPOB Masking End Line 1.
CLPOB Masking Start Line 2.
Must be set to 0.
CLPOB Masking End Line 2.
CLPOB Masking Start Line 3.
Must be set to 0.
CLPOB Masking End Line 3.
PBLK Masking Start Line 1.
Must be set to 0.
PBLK Masking End Line 1.
PBLK Masking Start Line 2.
Must be set to 0.
PBLK Masking End Line 2.
PBLK Masking Start Line 3.
Must be set to 0.
PBLK Masking End Line 3.
OD
) with respect to DCLK rising edge.
AD9923