SGTL5000XNLA3R2 Freescale, SGTL5000XNLA3R2 Datasheet - Page 48

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SGTL5000XNLA3R2

Manufacturer Part Number
SGTL5000XNLA3R2
Description
Manufacturer
Freescale
Datasheet

Specifications of SGTL5000XNLA3R2

Single Supply Voltage (typ)
1.8/2.5/3.3V
Lead Free Status / RoHS Status
Compliant

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48
SGTL500
FUNCTIONAL DEVICE OPERATION
PROGRAMMING EXAMPLES
BITS
6
5
4
3
2
1
0
INVERT_ADC_SAMPL
INVERT_ADC_DATA_
ADC_DITHEROFF
DAC_DOUBLE_I
DAC_DIS_RTZ
DAC_CLASSA
ADC_LESSI
E_CLOCK
TIMING
FIELD
RW
RW
RW
RW
RW
RW
RW
RW
RESET
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Double the output current of the DAC amplifier when it is in classA mode.
Turn off the return-to-zero in the DAC. In mode cases this will hurt the SNDR of the
DAC.
Turn off the classAB mode in the DAC amplifier. This mode should normally not be
used. The output current will not be high enough to support a full scale signal in this
mode.
Change the clock edge used for the ADC sampling.
Change the clock edge used for the analog to digital ADC data crossing
Drops ADC bias currents by 20%
Turns off the ADC dithering.
DEFINITION
Analog Integrated Circuit Device Data
Freescale Semiconductor

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