DS90C387AVJD National Semiconductor, DS90C387AVJD Datasheet - Page 6

• Manufacturer Part Number: DS90C387AVJD
• Manufacturer: National Semiconductor

Specifications of DS90C387AVJD

• Number Of Elements: 8
• Input Type: CMOS/TTL
• Operating Supply Voltage (typ): 3.3V
• Differential Input High Threshold Voltage: 100mV
• Diff. Input Low Threshold Volt: -100mV
• Output Type: Flat Panel Display
• Differential Output Voltage: 450mV
• Operating Temp Range: -10C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: TQFP
• Number Of Receivers: 48
• Number Of Drivers: 8
• Lead Free Status / RoHS Status: Not Compliant

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Symbol
CLHT
CHLT
RCOP
RCOH
RCOL
RSRC
RHRC
RPLLS
RPDD
RSKM
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Note 4: The Minimum and Maximum Limits are based on statistical analysis of the device performance over voltage and temperature ranges. This parameter is
functionally tested on Automatic Test Equipment (ATE). ATE is limited to 85MHz. A sample of characterization parts have been bench tested at 112MHz to verify
functional performance.
Note 5: The limits are based on bench characterization of the device’s jitter response over the power supply voltage range. Output clock jitter is measured with a
cycle-to-cycle jitter of
in the clock edge from most graphics VGA chips currently available. This parameter is used when calculating system margin as described in AN-1059.
Note 6: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account transmitter output pulse positions
(min and max) and the receiver input setup and hold time (internal data sampling window - RSPOS). This margin allows for LVDS interconnect skew, inter-symbol
interference (both dependent on type/length of cable) and clock jitter.
RSKM ≥ cable skew (type, length) + source clock jitter (cycle to cycle).
CMOS/TTL Low-to-High Transition Time (Figure 4), Rx data out
CMOS/TTL Low-to-High Transition Time (Figure 4), Rx clock out
CMOS/TTL High-to-Low Transition Time (Figure 4), Rx data out
CMOS/TTL High-to-Low Transition Time (Figure 4), Rx clock out
RxCLK OUT Period (Figure 7)
RxCLK OUT High Time (Figure 7)(Note 4)
RxCLK OUT Low Time (Figure 7)(Note 4)
RxOUT Setup to RxCLK OUT (Figure 7)(Note 4)
RxOUT Hold to RxCLK OUT (Figure 7)(Note 4)
Receiver Phase Lock Loop Set (Figure 9)
Receiver Powerdown Delay (Figure 11)
Receiver Skew Margin (Figure 12) (Notes 4, 6),
±
3ns applied to the input clock signal while data inputs are switching (see figures 15 and 16). A jitter event of 3ns, represents worse case jump
Parameter
6
f = 112 MHz
f = 85 MHz
f = 112 MHz
f = 85 MHz
f = 112 MHz
f = 85 MHz
f = 112 MHz
f = 85 MHz
f = 112 MHz
f = 100 MHz
f = 85MHz
f = 66MHz
8.928
4.75
Min
170
170
300
300
3.5
4.5
3.5
4.5
2.4
3.0
3.4
1.52
Typ
240
350
350
0.5
1.7
0.5
T
30.77
Max
2.0
1.0
2.0
1.0
10
1
Units
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ps
ps
ps
ps