HI-3582PQI-10 Holt Integrated Circuits, HI-3582PQI-10 Datasheet
HI-3582PQI-10
Specifications of HI-3582PQI-10
Related parts for HI-3582PQI-10
HI-3582PQI-10 Summary of contents
Page 1
... Timing is based Mega- hertz clock. Although the line driver shares a common substrate with the receivers, the design of the physical isolation does not allow parasitic crosstalk, and thereby achieves the same isolation as common hybrid layouts. FEATURES ! ARINC specification 429 compatible ! 3 ...
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... Latch enable for byte 1 entered from data bus to transmitter FIFO. Latch enable for byte 2 entered from data bus to transmitter FIFO. Must follow Transmitter ready flag. Goes low when ARINC word loaded into FIFO. Goes high after transmission and FIFO empty. Transmitter FIFO Half Full Transmitter FIFO Full -9 ...
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... Unscramble ARINC data HI-3582, HI-3583 STATUS REGISTER The HI-3582/HI-3583 contain a 9-bit status register which can be interrogated to determine the status of the ARINC receivers, data FIFOs and transmitter. The contents of the status register are is pulsed low. The output on BD00 - BD08 when the SEL = 0 ...
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... Additionally, for data bits, the One or Zero in the upper bits of the sampling shift registers must be followed by a Null in the lower bits within the data bit time. For a Null in the word gap, three consecutive Nulls must be found in both the upper and lower bits of the sampling shift register. In this manner the minimum pulse width is guaranteed ...
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... CR2-CR11, the received ARINC 32-bit word is then checked for correct decoding and label matching before being loaded into the receive FIFO. ARINC words which do not meet the necessary 9th and 10th ARINC bit or label matching are ignored and are not loaded into the receive FIFO. The following table describes this operation ...
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... PL2 the 31 bit word (or 32 bit word if CR4=0) in the next available position of the FIFO. If TX/R, the transmitter ready flag is high (FIFO empty), then words, each bits long, may be loaded. If TX/R is low, then only the available positions may be loaded. If all 32 positions are full, the FIFO ignores further attempts to load data ...
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... The parity generator counts the Ones in the 31-bit word. If control register bit CR12 is set low, the 32nd bit transmitted will make parity odd. If the control bit is high, the parity is even. Setting CR4 to a Zero bypasses the parity generator, and allows 32 bits of data to be transmitted. ...
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... BIT 31 BIT 32 D D/R DON'T CARE SEL EN DATA BUS t ENDATA DATA BUS PL1 PL2 TX/R, FFT HFT DATA BUS CWSTR HI-3582, HI-3583 DATA RATE - EXAMPLE PATTERN DATA DATA NULL NULL BIT 32 BIT 31 RECEIVER OPERATION t t SELEN t SELEN ENSEL t t ENEN D/REN t ...
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... PL t CWSTR CWSTR EN1 or EN2 t CWHLD t CWSET DATA BUS Set CR1=1 Label #1 t ENDATA HI-3582, HI-3583 STATUS REGISTER READ CYCLE DON'T CARE t SELEN DATA VALID t ENDATA CONTROL REGISTER READ CYCLE DON'T CARE t SELEN DATA VALID t ENDATA LABEL MEMORY LOAD SEQUENCE Label #2 ...
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... DIFF (TXAOUT) - TXBOUT) 10% one level RIN BIT 32 D D/R D/REN EN t SELEN SEL DON'T CARE t ENPL PL1 PL2 TXR ENTX TXAOUT TXBOUT HI-3582, HI-3583 TRANSMITTING DATA ARINC BIT ARINC BIT DATA DATA BIT 2 BIT 1 +5V -5V +5V - +10V 90 10% rx 90% zero level ...
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... HEAT SINK - CHIP-SCALE PACKAGE ONLY The HI-3582PCSI/T/M and HI-3583PCI/T/M use a 44-pin plastic chip-scale package. This package has a metal heat sink pad on its bottom surface. This heat sink is electrically connected to the die. To enhance thermal dissipation, the HI-3582, HI-3583 Power Dissipation at 25°C Plastic Quad Flat Pack ...
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... Differential C (RIN1A to RIN1B, RIN2A to RIN2B GND Input Voltage Input Voltage Input Sink I IH Input Source I IL Input Voltage Input Sink I IH Input Source One or zero V No load and magnitude at pin, DOUT Null V V NOUT One or zero V No load and magnitude at pin, ...
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... Delay - 32nd ARINC Bit to TX/R HIGH Spacing - TX/R HIGH to ENTX LOW LINE DRIVER OUTPUT TIMING Delay - ENTX HIGH to TXAOUT or TXBOUT: High Speed Delay - ENTX HIGH to TXAOUT or TXBOUT: Low Speed Line driver transition differential times: (High Speed, control register CR13 = Logic 0) (Low Speed, control register CR13 = Logic 1) ...
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... ADDITIONAL HI-3582 / HI-3583 PIN CONFIGURATIONS BD15 - 16 BD14 - 17 BD13 - 18 BD12 - 19 BD11 - 20 ORDERING INFORMATION HI - 35xx PART NUMBER No dash number -10 (See Note 1) PART NUMBER PART NUMBER PART NUMBER PART NUMBER HI-3582, HI-3583 FF1 - 8 HF1 - 9 D/ HI-3582CJI FF2 - 11 HI-3582CJT HF2 - 12 HI-3582CJM SEL - 13 & EN1 - 14 EN2 ...
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... REVISION HISTORY Revision Date Page Description of Change DS3582, Rev. H 07/21/ Added “M” process part numbers to Pin Descriptions and Ordering Information HI-3582, HI-3583 and clarified temperature ranges in Features HOLT INTEGRATED CIRCUITS 15 ...
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... HI-3582 / HI-3583 PACKAGE DIMENSIONS 52-PIN J-LEAD CERQUAD 7 8 .019 .002 (.483 .051) 52-PIN PLASTIC QUAD FLAT PACK (PQFP) .520 BSC SQ (13.2) .063 (1.6) See Detail A .084 .013 ± (2.13 ± .32) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance ...
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... HI-3582 / HI-3583 PACKAGE DIMENSIONS 64-PIN PLASTIC CHIP-SCALE PACKAGE .354 BSC (9.00) .354 Top View BSC (9.00) .039 max (1.00) Heat sink pad on bottom of package. Heat sink can float or can be connected to V+. DO NOT connect heat sink to VDD, GND or V- .281 ± .006 (7.15 ± ...