XC3S500E-4FT256I Xilinx Inc, XC3S500E-4FT256I Datasheet - Page 116

• Manufacturer Part Number: XC3S500E-4FT256I
• Description: FPGA Spartan®-3E Family 500K Gates 10476 Cells 572MHz 90nm (CMOS) Technology 1.2V 256-Pin FTBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S500E-4FT256I

• Package: 256FTBGA
• Family Name: Spartan®-3E
• Device Logic Cells: 10476
• Device Logic Units: 1164
• Device System Gates: 500000
• Number Of Registers: 9312
• Maximum Internal Frequency: 572 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 190
• Ram Bits: 368640
• Number Of Logic Elements/cells: 10476
• Number Of Labs/clbs: 1164
• Total Ram Bits: 368640
• Number Of I /o: 190
• Number Of Gates: 500000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-LBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Functional Description
116
05/30/06
10/02/06
11/09/06
03/16/07
05/29/07
04/18/08
08/26/09
Date
Version
3.2.1
3.3
3.4
3.5
3.6
3.7
3.8
Corrected various typos and incorrect links.
Clarified that the block RAM
the Industrial temperature range.
Updated the description of the
Alignment is no longer supported. Updated
input voltage tolerance. Replaced missing text in
Flash devices in
Flash in-system
software for STMicro and Atmel SPI PROMs. Updated
1 is in full production. Freshened various hyper links. Promoted Module 2 to Production
status.
Added information about new Spartan-3 Generation user guides
Available). Added cross-references to UG331: Spartan-3 Generation FPGA User Guide
and to UG332: Spartan-3 Generation Configuration User Guide. Added note about possible
JTAG configuration issues when the FPGA mode pins are set for Master mode and using
software prior to ISE 9.1.01i
pull-up resistors, including in
LDC[2:0] and HDC pins during
in this configuration mode.
Added information about HSWAP and PCI differences between steppings to
Removed “Performance Differences between Global Buffers” to match improved specs in
Module 3. Updated PROG_B pulse width descriptions to match specification in Module 3.
Corrected
recommended pull-up on DONE in
Persist of pins A20-A23. Updated Stepping description in
Stepping 1 is in production today. Updated links.
Added a frequency limitation to
a frequency limitation. Added a
page
the flash read access times in
Configuration Sequence, page
page
first paragraph in
62. Updated a Flash vendor name in
112. Revised the second paragraph in
Figure 6
Programming Support
Table
Ordering a Later Stepping, page
to show six taps and updated associated text. Added note for
www.xilinx.com
53. Updated parallel NOR Flash devices in
Readback
(JTAG
Figure
Input Delay
Table 62, page
Slave Parallel Mode
Equation 6, page
Spread Spectrum, page 58
103. Revised the first paragraph in
Table 55
Mode). Removed a few lingering references to “weak”
12. Removed vestigial references regarding the
feature is available either on the -5 speed grade or
Revision
was added beginning with ISE 8.1i iMPACT
Table 61, page
Functions. The
Figure
Production Stepping, page
and elsewhere. Added a caution regarding
90. Revised the first paragraph in
Clock
57. Added a new
5. Updated
configuration. These pins are not used
113.
Buffers/Multiplexers. Updated SPI
Table 71
Table 71
90. Removed the < symbol from
ODDR2
paragraph. Added
DS312-2 (v3.8) August 26, 2009
Table 6
and
(Design Documentation
Equation 7, page 57
Table
to note that only
flip-flop with C0 or C1
Power-On Behavior,
Table 72
for improved PCI
Product Specification
61. Direct, SPI
113. Revised the
Table
as Stepping
Table 42,
71.
with
R