LFE2M20E-5F256I LATTICE SEMICONDUCTOR, LFE2M20E-5F256I Datasheet - Page 32

• Manufacturer Part Number: LFE2M20E-5F256I
• Description: FPGA LatticeECP2M Family 19000 Cells 90nm (CMOS) Technology 1.2V 256-Pin FBGA
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LFE2M20E-5F256I

• Package: 256FBGA
• Family Name: LatticeECP2M
• Device Logic Units: 19000
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 140
• Ram Bits: 1246208
• In System Programmability: Yes

Lattice Semiconductor
LatticeECP2/M DSP Performance
Table 2-11 lists the maximum performance in millions of MAC operations per second (MMAC) for each member of
the LatticeECP2/M family.
Table 2-11. DSP Performance
For further information about the sysDSP block, please see the list of additional technical information at the end of
this data sheet.
Programmable I/O Cells (PIC)
Each PIC contains two PIOs connected to their respective sysI/O buffers as shown in Figure 2-28. The PIO Block
supplies the output data (DO) and the tri-state control signal (TO) to the sysI/O buffer and receives input from the
buffer. Table 2-12 provides the PIO signal list.
ECP2M100
ECP2M20
ECP2M35
ECP2M50
ECP2M70
ECP2-12
ECP2-20
ECP2-35
ECP2-50
ECP2-70
ECP2-6
Device
DSP Block
2-29
18
22
22
24
42
3
6
7
8
6
8
LatticeECP2/M Family Data Sheet
DSP Performance
GMAC
10.4
23.4
28.6
10.4
28.6
31.2
54.6
3.9
7.8
9.1
7.8
Architecture