LTC1553LCSW#TRM Linear Technology, LTC1553LCSW#TRM Datasheet - Page 13

• Manufacturer Part Number: LTC1553LCSW#TRM
• Manufacturer: Linear Technology

Specifications of LTC1553LCSW#TRM

• Lead Free Status / RoHS Status: Not Compliant

APPLICATIONS
If the OUTEN pin is low, G1 and G2 are both held low to
prevent output voltage undershoot. As V
power up from a 0V condition, an internal undervoltage
lockup circuit prevents G1 and G2 from going high until
V
ground potential, the SS is forced to ground potential
internally. SS clamps the COMP pin low and prevents the
drivers from turning on. On power-up or recovery from
thermal shutdown, the drivers are designed such that G2
is held low until G1 first goes high.
Power MOSFETs
Two N-channel power MOSFETs are required for most
LTC1553L circuits. Logic level MOSFETs should be used
and they should be selected based on on-resistance con-
siderations. R
output voltage, allowable power dissipation and maxi-
mum required output current. In a typical LTC1553L buck
converter circuit the average inductor current is equal to
the output load current. This current is always flowing
through either Q1 or Q2 with the power dissipation split up
according to the duty cycle:
The R
be calculated by rearranging the relation P = I
CC
OPTIONAL FOR V
DC Q
DC Q
reaches about 3.5V. If V
1N5243B
13V
DS(ON)
LTC1553L
1
2
required for a given conduction loss can now
V
1
IN
DS(ON)
2
V
Figure 7. Doubling Charge Pump
OUT
> 5V
IN
PV
V
CC
V
OUT
IN
U
should be chosen based on input and
G1
G2
20
INFORMATION
1
U
V
IN
CC
V
1N5817
powers up while PV
0.1 F
IN
V
OUT
W
V
IN
Q2
Q1
L
O
CC
2
+
+
U
and PV
R.
CC
C
C
1553L F07
IN
OUT
V
OUT
is at
CC
P
efficiency or allowable thermal dissipation. A typical high
efficiency circuit designed for Pentium II with a 5V input
and a 2.8V, 11.2A output might allow no more than 4%
efficiency loss at full load for each MOSFET. Assuming
roughly 90% efficiency at this current level, this gives a
P
and a required R
Note also that while the required R
large MOSFETs, the dissipation numbers are only 1.39W
per device or less––large TO-220 packages and heat sinks
are not necessarily required in high efficiency applica-
tions. Siliconix Si4410DY or International Rectifier IRF7413
(both in SO-8) or Siliconix SUD50N03 or Motorola
MTD20N03HDL (both in D PAK) are small footprint sur-
face mount devices with R
of gate drive that work well in LTC1553L circuits. With
higher output voltages, the R
significantly lower than that for Q2. These conditions can
often be met by paralleling two MOSFETs for Q1 and using
a single device for Q2. Note that using a higher P
in the R
cost and circuit efficiency while increasing MOSFET heat
sink requirements.
MAX
MAX
R
R
[(2.8)(11.2A/0.9)(0.04)] = 1.39W per FET
R
R
DS ON Q
DS ON Q
DS ON Q
DS ON Q
value of:
should be calculated based primarily on required
DS(ON)
1
2
1
2
calculations will generally decrease MOSFET
DC Q
DS(ON)
DC Q
2 8
5
5
V
P
V
P
V
MAX Q
MAX Q
5
1
2
V
1 39
2 8
11 2
of:
I
DS(ON)
MAX
1 39
I
V
MAX
1
2
W
A
DS(ON)
11 2
W
2
2
2
values below 0.03 at 5V
A
0 019
DS(ON)
of Q1 may need to be
V
2
V
V
IN
OUT MAX
IN
V
LTC1553L
IN
0 025
P
values suggest
MAX Q
V
I
P
OUT MAX
MAX Q
MAX
1
2
I
13
2
value
2