AD9858BSV Analog Devices Inc, AD9858BSV Datasheet - Page 25

• Manufacturer Part Number: AD9858BSV
• Manufacturer: Analog Devices Inc

Specifications of AD9858BSV

• Lead Free Status / RoHS Status: Not Compliant

CFR[4:2]: Power-Down Bits
Active high (Logic 1) powers down the respective function.
Writing a Logic 1 to all three bits causes the device to enter full
sleep mode.
CFR[4] is used to shut down the analog mixer stage (default = 1).
CFR[3] is used to shut down the phase detector and charge
pump circuitry (default = 1).
CFR[2] is used to shut down the DDS core and DAC and to
stop all internal clocks except SYNCLK (default = 0).
CFR[1]: SDIO Input Only
When CFR[1] = 0 (default), the SDIO pin has bidirectional
operation (2-wire serial programming mode).
When CFR[1] = 1, the serial data I/O pin (SDIO) is configured
as an input only pin (3-wire serial programming mode).
CFR[0]: LSB First
This bit has an effect on device operation only if the I/O port is
configured as a serial port.
When CFR[0] = 0 (default), MSB first format is active.
When CFR[0] = 1, LSB first format is active.
OTHER REGISTERS
Delta Frequency Tuning Word (DFTW)
The DFTW register comprises four bytes. The contents of the
DFTW are applied to the input of the frequency accumulator.
When the device is in the frequency sweep mode, the output of
the frequency accumulator is added to the frequency tuning
word and fed to the phase accumulator. This provides the
frequency sweep capability of the AD9858.
Delta Frequency Ramp Rate Word (DFRRW)
The DFRRW comprises two bytes. The DFRRW is a 16-bit
unsigned number used to clock the frequency accumulator.
USER PROFILE REGISTERS
The user profile registers are comprised of the four frequency
tuning words and four phase offset words. Each pair of
frequency and phase registers forms a configurable user profile,
selected by the user profile pins.
User Profiles
The AD9858 features four user profiles (0 to 3) that are selected
by the profile select pins (PS0 and PS1) on the device. Each
profile has its own frequency tuning word. This allows the user
to load a different frequency tuning word into each profile,
which can then be selected as desired by the profile select pins.
This makes it possible to hop among the different frequencies at
rates up to 1/16 of the SYSCLK while in single-tone mode.
Rev. C | Page 25 of 32
The AD9858 also provides a 14-bit phase offset word (POW)
for each profile. The value in this register is a 14-bit unsigned
number (POW) that represents the proportional (PO/2
offset to be added to the instantaneous phase value. This allows
the phase of the output signal to be adjusted in fine increments
of phase (about 0.022°). It is possible to update the FTW and
POW of any profile while the AD9858 is operating at the
frequency specified by another profile and then switch to the
profile containing the newly loaded frequency. Changing the
current profile updates both parameters so care must be taken
to ensure that no unwanted parameter changes take place.
It is also possible to repeatedly write a new frequency into the
FTW register of a selected profile and to jump to the new
frequency by strobing the frequency update pin (FUD). This
allows hopping to arbitrary frequencies but is limited in the rate
at which this can be accomplished by the speed of the I/O port
(100 MHz in parallel mode) and the necessity to transfer several
bytes of data for each new frequency tuning word. This can be
accomplished rapidly enough for many applications.
Phase Offset Control
A 14-bit phase offset (θ) can be added to the output of the phase
accumulator by means of the phase offset words stored in the
memory registers. This feature provides the user with three
different methods of phase control.
The first method is a static phase adjustment, where a fixed phase
offset is loaded into the appropriate phase offset register and left
unchanged. The result is that the output signal is offset by a
constant angle relative to the nominal signal. This allows the user to
phase align the DDS output with an external signal, if necessary.
The second method of phase control is where the user regularly
updates the appropriate phase offset register via the I/O port. By
properly modifying the phase offset as a function of time, the
user can implement a phase modulated output signal. The rate
at which phase modulation can be performed is limited by both
the speed of the I/O port and the frequency of SYSCLK.
The third method of phase control involves the profile registers,
in which the user loads up to four different phase offset values
into the appropriate profiles. The user can then select among
the four preloaded phase offset values via the AD9858 profile
select pins. Therefore, the phase changes are accomplished by
driving the hardware pins rather than writing to the I/O port,
thereby avoiding the speed limitation imposed by the I/O port.
However, this method is restricted to only four phase offset
values (one phase offset value per profile). Each profile has an
associated frequency and phase value. Changing the current
profile updates both parameters; therefore, care must be taken
to ensure that no unwanted parameter changes take place.
The phase offset value is routed through a unit delay (z
This is done to ensure that updates of the phase offset values
exhibit the same amount of latency as updates of the frequency
tuning word.
AD9858
–1
14
) block.
) phase