AM50DL128BG70I Spansion Inc., AM50DL128BG70I Datasheet
AM50DL128BG70I
Specifications of AM50DL128BG70I
Related parts for AM50DL128BG70I
AM50DL128BG70I Summary of contents
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Am50DL128BG Data Sheet July 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig- inally developed the specification, ...
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PRELIMINARY Am50DL128BG Stacked Multi-Chip Package (MCP) Flash Memory and SRAM Two Am29DL640G 64 Megabit ( 8-Bit 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memories and 32 Mbit ( 16-Bit) Pseudo Static RAM with Page ...
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GENERAL DESCRIPTION Am29DL640G Features The Am29DL640G megabit, 3.0 volt-only flash memory device, organized as 4,194,304 words of 16 bits each or 8,388,608 bytes of 8 bits each. Word mode data appears on DQ15–DQ0; byte mode data appears ...
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TABLE OF CONTENTS Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5 MCP Block Diagram . . . . . . . . . ...
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Flash Erase And Programming Performance . . . 59 Latchup Characteristics . . . . . . . . . . . . . . . . . . . 59 Package Pin Capacitance . . . . . . ...
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PRODUCT SELECTOR GUIDE Part Number Speed Standard Voltage Range: Options V = 2.7–3 Max Access Time, ns Page Access Time (pSRAM), ns CE#f Access, ns OE# Access, ns MCP BLOCK DIAGRAM CE#f1 A21 to A0 A-1 WP#/ACC RESET# ...
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FLASH MEMORY BLOCK DIAGRAM Mux A21–A0 RY/BY# A21–A0 STATE RESET# CONTROL WE# & CE# COMMAND REGISTER BYTE# WP#/ACC DQ15–DQ0 A21–A0 Mux OE# BYTE# Bank ...
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CONNECTION DIAGRAM LB UB A18 A17 DQ1 ...
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PIN DESCRIPTION A20– Address Inputs (Common) A21, A Address Inputs (Flash) DQ15–DQ0 = 16 Data Inputs/Outputs (Common) CE#f1 = Chip Enable 1 (Flash 1) CE#f2 = Chip Enable 2 (Flash 2) CE#1s = Chip Enable 1 ...
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... January 8, 2003 TAPE AND REEL inches inches TEMPERATURE RANGE I = Industrial (– +85 C) SPEED OPTION See “Product Selector Guide” on page 5. PROCESS TECHNOLOGY G = 0.17 µm PSEUDO SRAM DEVICE DENSITY Mbits Order Number Am50DL128BG70I Am50DL128BG85I Am50DL128BG Valid Combinations Package Marking T, S M500000000 T, S M500000001 9 ...
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MCP DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory loca- tion. The register is a ...
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Table 1. Device Bus Operations—Flash Word Mode, CIOf = V CE#f CE#f Operation Active Inactive CE1#s (Notes 1, 2) (Note 3) (Note 8) Read from L H Active Flash (Note 9) (Note 8) Write to Active L H Flash (Note ...
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Table 2. Device Bus Operations—Flash Byte Mode, CIOf = V CE#f CE#f Operation Active Inactive CE2s (Notes 1, 2) (Note 3) (Note 8) H Read from L Flash (Note 9) H (Note 8) H Write to Flash L (Note 9) ...
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FLASH DEVICE BUS OPERATIONS Word/Byte Configuration The CIOf pin controls whether the device data I/O pins operate in the byte or word configuration. If the CIOf pin is set at logic ‘1’, the device is in word configura- tion, DQ15–DQ0 ...
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I f and the table represent the cur- CC6 CC7 rent specifications for read-while-program and read-while-erase, respectively. Standby Mode When the system is not reading or writing to ...
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Table 3. Am29DL640G Sector Architecture Sector Address Bank Sector A21–A12 SA0 0000000000 SA1 0000000001 SA2 0000000010 SA3 0000000011 SA4 0000000100 SA5 0000000101 SA6 0000000110 SA7 0000000111 SA8 0000001xxx SA9 0000010xxx SA10 0000011xxx Bank 1 SA11 0000100xxx SA12 0000101xxx SA13 0000110xxx ...
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Table 3. Am29DL640G Sector Architecture (Continued) Sector Address Bank Sector A21–A12 SA23 0010000xxx SA24 0010001xxx SA25 0010010xxx SA26 0010011xxx SA27 0010100xxx SA28 0010101xxx SA29 0010110xxx SA30 0010111xxx SA31 0011000xxx SA32 0011001xxx SA33 0011010xxx SA34 0011011xxx SA35 0011000xxx SA36 0011101xxx SA37 ...
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Table 3. Am29DL640G Sector Architecture (Continued) Sector Address Bank Sector A21–A12 SA71 1000000xxx SA72 1000001xxx SA73 1000010xxx SA74 1000011xxx SA75 1000100xxx SA76 1000101xxx SA77 1000110xxx SA78 1000111xxx SA79 1001000xxx SA80 1001001xxx SA81 1001010xxx SA82 1001011xxx SA83 1001100xxx SA84 1001101xxx SA85 ...
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Table 3. Am29DL640G Sector Architecture (Continued) Sector Address Bank Sector A21–A12 SA119 1110000xxx SA120 1110001xxx SA121 1110010xxx SA122 1110011xxx SA123 1110100xxx SA124 1110101xxx SA125 1110110xxx SA126 1110111xxx SA127 1111000xxx SA128 1111001xxx SA129 1111010xxx Bank 4 SA130 1111011xxx SA131 1111100xxx SA132 ...
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Sector/Sector Block Protection and Unprotection (Note: For the following discussion, the term “sector” applies to both sectors and sector blocks. A sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see ...
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If the system asserts V on the WP#/ACC pin, the de- IH vice reverts to whether sectors 0, 1, 140, and 141 were last set to be protected or unprotected. That is, sector protection or unprotection for these sectors de- ...
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START PLSCNT = 1 RESET Wait First Write Temporary Sector Cycle = 60h? Unprotect Mode Yes Set up sector address Sector Protect: Write 60h to sector address with ...
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SecSi™ (Secured Silicon) Sector Flash Memory Region The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The SecSi Sector is 256 bytes in length, and uses a ...
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START If data = 00h, RESET# = SecSi Sector unprotected. If data = 01h, SecSi Sector is Wait 1 s protected. Write 60h to any address Remove V from RESET# Write 40h to ...
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Addresses Addresses (Word Mode) (Byte Mode) 10h 20h 11h 22h 12h 24h 13h 26h 14h 28h 15h 2Ah 16h 2Ch 17h 2Eh 18h 30h 19h 32h 1Ah 34h Addresses Addresses (Word Mode) (Byte Mode) 1Bh 36h 1Ch 38h 1Dh 3Ah ...
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Addresses Addresses (Word Mode) (Byte Mode) 27h 4Eh 28h 50h 29h 52h 2Ah 54h 2Bh 56h 2Ch 58h 2Dh 5Ah 2Eh 5Ch 2Fh 5Eh 30h 60h 31h 62h 32h 64h 33h 66h 34h 68h 35h 6Ah 36h 6Ch 37h 6Eh ...
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Table 11. Primary Vendor-Specific Extended Query Addresses Addresses (Word Mode) (Byte Mode) 40h 80h 41h 82h 42h 84h 43h 86h 44h 88h 45h 8Ah 46h 8Ch 47h 8Eh 48h 90h 49h 92h 4Ah 94h 4Bh 96h 4Ch 98h 4Dh 9Ah ...
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FLASH COMMAND DEFINITIONS Writing specific address and data commands or se- quences into the command register initiates device op- erations. Table 12 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper ...
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Sector command sequence. The device continues to access the SecSi Sector region until the system is- sues the four-cycle Exit SecSi Sector command se- quence. The Exit SecSi Sector command sequence returns the device to normal operation. The SecSi Sector ...
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Write Program Command Sequence Data Poll from System Embedded Program algorithm in progress Verify Data? No Increment Address Last Address? Programming Completed Note: See Table 12 for program command sequence. Figure 4. Program Operation Chip Erase Command Sequence Chip erase ...
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The system can de- termine the status of the erase operation by reading DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. Refer to the Flash Write Operation Status section for information on these status ...
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Table 12. Am29DL640G Command Definitions Command Sequence (Note 1) Addr Read (Note Reset (Note 7) 1 XXX Word 555 Manufacturer ID 4 Byte AAA Word 555 Device ID (Note 9) 6 Byte AAA SecSi Sector Factory Word ...
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FLASH WRITE OPERATION STATUS The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 13 and the following subsections describe the function of these bits. DQ7 and DQ6 ...
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RY/BY#: Ready/Busy# The RY/BY dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since ...
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DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indi- cates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit ...
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Status Embedded Program Algorithm Standard Mode Embedded Erase Algorithm Erase Suspended Sector Erase-Suspend- Erase Read Suspend Non-Erase Mode Suspended Sector Erase-Suspend-Program Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . . . – +125 C Ambient Temperature with Power Applied . . . . . . . . ...
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FLASH DC CHARACTERISTICS CMOS Compatible Parameter Parameter Description Symbol I Input Load Current LI I RESET# Input Load Current LIT I Reset Leakage Current LR I Output Leakage Current LO I ACC Input Leakage Current LIA Flash V Active Read ...
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DC & OPERATING CHARACTERISTICS Parameter Parameter Description Symbol I Input Leakage Current LI I Output Leakage Current Operating Current CC1 Page Access Operating I s CC2 Current V Output Low Voltage OL V Output High Voltage ...
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FLASH DC CHARACTERISTICS Zero-Power Flash 500 1000 Note: Addresses are switching at 1 MHz Figure 10. I Current vs. Time (Showing Active and Automatic Sleep Currents) CC1 ...
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TEST CONDITIONS Device Under Test C 6 Note: Diodes are IN3064 or equivalent Figure 12. Test Setup KEY TO SWITCHING WAVEFORMS WAVEFORM Don’t Care, Any Change Permitted 3.0 V 1.5 V Input 0.0 V Figure 13. Input Waveforms ...
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AC CHARACTERISTICS CE#s Timing Parameter JEDEC Std Description — t CE#s Recover Time CCR CE#f CE1#s CE2s Figure 14. Timing Diagram for Alternating January 8, 2003 Test Setup ...
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FLASH AC CHARACTERISTICS Read-Only Operations Parameter JEDEC Std. Description t t Read Cycle Time (Note 1) AVAV Address to Output Delay AVQV ACC t t Chip Enable to Output Delay ELQV Output Enable to ...
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FLASH AC CHARACTERISTICS Hardware Reset (RESET#) Parameter JEDEC Std RESET# Pin Low (During Embedded Algorithms) t Ready to Read Mode (See Note) RESET# Pin Low (NOT During Embedded t Ready Algorithms) to Read Mode (See Note) t RESET# Pulse Width ...
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FLASH AC CHARACTERISTICS Word/Byte Configuration (CIOf) Parameter JEDEC Std Description t t CE#f to CIOf Switching Low or High ELFL/ ELFH t CIOf Switching Low to Output HIGH Z FLQZ t CIOf Switching High to Output Active FHQV CE#f OE# ...
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FLASH AC CHARACTERISTICS Erase and Program Operations Parameter JEDEC Std Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL AS t Address Setup Time to OE# low during toggle bit polling ASO t ...
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FLASH AC CHARACTERISTICS Program Command Sequence (last two cycles Addresses 555h CE#f t GHWL OE# WE Data RY/BY VCS Notes program address program data Illustration ...
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FLASH AC CHARACTERISTICS Erase Command Sequence (last two cycles Addresses 2AAh CE#f t GHWL OE WE Data 55h RY/BY# t VCS Notes: 1. SADD = sector address (for Sector ...
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FLASH AC CHARACTERISTICS t WC Valid PA Addresses t AH CE#f OE WE# t WPH t DS Valid Data In WE# Controlled Write Cycle Figure 22. Back-to-back Read/Write Cycle Timings t RC Addresses VA t ACC t CE ...
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FLASH AC CHARACTERISTICS Addresses CE#f t OEH WE# OE Valid Data DQ6/DQ2 RY/BY# Note Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data ...
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FLASH AC CHARACTERISTICS Temporary Sector Unprotect Parameter JEDEC Std Description t V Rise and Fall Time (See Note) VIDR Rise and Fall Time (See Note) VHH HH RESET# Setup Time for Temporary Sector t RSP Unprotect RESET# ...
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FLASH AC CHARACTERISTICS RESET# SADD, A6, A1, A0 Sector/Sector Block Protect or Unprotect Data 60h 1 µs CE#f WE# OE# * For sector protect For sector unprotect, ...
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FLASH AC CHARACTERISTICS Alternate CE#f Controlled Erase and Program Operations Parameter JEDEC Std Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL Address Hold Time ELAX Data ...
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FLASH AC CHARACTERISTICS 555 for program 2AA for erase Addresses WE# OE# CE Data t RH RESET# RY/BY# Notes: 1. Figure indicates last two bus cycles of a program or erase operation ...
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AC CHARACTERISTICS Read Cycle Parameter Description Symbol t Read Cycle Time RC t Address Access Time ACC t Chip Enable Access Time CO t Output Enable Access Time OE t Data Byte Control Access Time BA t Chip Enable ...
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AC CHARACTERISTICS Addresses Addresses A20 to A3 CE#1s CE2s OE# WE# LB#, UB# D OUT DQ15 to DQ0 Notes and t are defined as the time at which OD, ODo ...
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AC CHARACTERISTICS Write Cycle Parameter Description Symbol t Write Cycle Time WC t Write Pulse Time WP t Chip Enable to End of Write CW t Data Byte Control to End of Write BW t Address Setup Time AS ...
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AC CHARACTERISTICS Addresses A20 WE# CE# CE2s LB#, UB# D High-Z OUT DQ15 to DQ0 D IN (Note 1) DQ15 to DQ0 Notes the device is using the I/Os to output ...
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AC CHARACTERISTICS Addresses A20 WE# CE# CE2s UB#, LB# D High-Z OUT DQ15 to DQ0 D IN DQ15 to DQ0 Notes the device is using the I/Os to output data, input ...
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FLASH ERASE AND PROGRAMMING PERFORMANCE Parameter Sector Erase Time Chip Erase Time Byte Program Time Accelerated Byte/Word Program Time Word Program Time Byte Mode Chip Program Time (Note 3) Word Mode Notes: 1. Typical program and erase times assume the ...
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DATA RETENTION Parameter Parameter Description Symbol V V for Data Retention Data Retention Current DR t CE2 Setup Time CS t CE2 Hold Time CH t CE2 Pulse Width DPD t CE2 Hold from CE#1 CHC ...
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ADDRESS SKEW CE#1s WE# Address Note: If multiple invalid address cycles shorter than t cycle over t is required during that period. RC min CE#1s WE# Address Note: If multiple invalid address cycles shorter than t cycle over t ...
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PHYSICAL DIMENSIONS FTA073—73-Ball Fine-Pitch Grid Array 0.15 C (2X) INDEX MARK PIN A1 CORNER 10 TOP VIEW SIDE VIEW 6 b 73X 0. 0. PACKAGE FTA ...
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REVISION SUMMARY Revision A (March 8, 2002) Initial release. Revision A+1 (March 20, 2002) Physical Dimensions Drawing, tables, and notes were replaced with up- dated versions. Revision A+2 (December 11, 2002) Distinctive Characteristics Corrected cycle specifications per sector. Pin Description ...