AT52BR1664-90CU Atmel, AT52BR1664-90CU Datasheet - Page 9

• Manufacturer Part Number: AT52BR1664-90CU
• Manufacturer: Atmel

Specifications of AT52BR1664-90CU

• Operating Supply Voltage (max): 3.3V
• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

2212C–STKD–09/02
must be used as shown in the “Command Definition in Hex” table on page 13. Data bit D1
must be zero during the fourth bus cycle. All other data bits during the fourth bus cycle are
don’t cares. To determine whether block B is locked out, the Product ID Entry command is
given followed by a read operation from address 80H. If data bit D1 is zero, block B is locked.
If data bit D1 is one, block B can be reprogrammed. Please see the “Protection Register
Addressing Table” on page 14 for the address locations in the protection register. To read the
protection register, the Product ID Entry command is given followed by a normal read opera-
tion from an address within the protection register. After determining whether block B is
protected or not, or reading the protection register, the Product ID Exit command must be
given prior to performing any other operation.
RDY/BUSY: An open-drain READY/BUSY output pin provides another method of detecting
the end of a program or erase operation. RDY/BUSY is actively pulled low during the internal
program and erase cycles and is released at the completion of the cycle. The open-drain con-
nection allows for OR-tying of several devices to the same RDY/BUSY line. Please see
“Status Bit Table” on page 12 for more details.
HARDWARE DATA PROTECTION: The Hardware Data Protection feature protects against
inadvertent programs to the 16-megabit Flash in the following ways: (a) V
below 1.8V (typical), the program function is inhibited. (b) V
reached the V
gramming. (c) Program inhibit: holding any one of OE low, CE high or WE high inhibits
program cycles. (d) Noise filter: pulses of less than 15 ns (typical) on the WE or CE inputs will
not initiate a program cycle. (e) Program inhibit: V
once V
INPUT LEVELS: While operating with a 2.7V to 3.6V power supply, the address inputs and
control inputs (OE, CE and WE) may be driven from 0 to 5.5V without adversely affecting the
operation of the device. The I/O lines can only be driven from 0 to V
OUTPUT LEVELS: For the Flash, output high levels (V
For 2.7V - 3.6V output levels, V
must be regulated to 2.0V ± 10%, while V
power).
PP
has reached 1.65V, program and erase operations can occur after 100 ns.
CC
sense level, the device will automatically time out 10 ms (typical) before pro-
CCQ
must be tied to V
CC
must be regulated to 2.7V - 3.0V (for minimum
AT52BR1662(T)/1664(T)
PP
is less than V
CC
OH
. For 1.8V - 2.2V output levels, V
) are equal to V
CC
power-on delay: once V
ILPP
CC
. (f) V
+ 0.6V.
CCQ
PP
CC
- 0.2V (not V
power-on delay:
sense: if V
CC
CC
has
CC
CCQ
is
).
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