5962-8751503LA E2V, 5962-8751503LA Datasheet - Page 9
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5962-8751503LA
Manufacturer Part Number
5962-8751503LA
Description
Manufacturer
E2V
Datasheet
1.5962-8751503LA.pdf
(16 pages)
Specifications of 5962-8751503LA
Lead Free Status / RoHS Status
Not Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
DSCC FORM 2234
APR 97
in 1.2 herein. In addition, the manufacturer's PIN may also be marked. For packages where the entire SMD PIN number is not
feasible due to space limitations, the manufacturer has the option of not marking the "5962-" on the device.
to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a "Q" or "QML" certification mark in
accordance with MIL-PRF-38535 to identify when the QML flow option is used.
manufacturer prior to delivery.
specified in 4.4 herein.
procedures and characteristics specified in 4.5 herein.
4.5 herein) to specified program or erased (see 4.4 herein). As a minimum, verification shall consist of performing a funtional
test (subgroup 7) to verify that all bits are in the proper state. Any bit that does not verify to be in the proper state shall constitute
a device failure, and shall be removed from the lot.
approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to
listing as an approved source of supply shall affirm that the manufacturer's product meets the requirements of MIL-PRF-38535,
appendix A and the requirements herein.
with each lot of microcircuits delivered to this drawing.
facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the
reviewer.
prior to quality conformance inspection. The following additional criteria shall apply:
3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed
3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance
3.6 Processing EPROMS. All testing requirements and quality assurance provisions herein shall be satisfied by the
3.6.1 Erasure of EPROMS. When specified, devices shall be erased in accordance with the procedures and characteristics
3.6.2 Programmability of EPROMS. When specified, devices shall be programmed to the specified pattern using the
3.6.3 Verification of erasure of programmed EPROMS. When specified, devices shall be verified as either programmed (see
3.7 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an
3.8 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided
3.9 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing.
3.10 Verification and review. DSCC, DSCC's agent, and the acquiring activity retain the option to review the manufacturer's
4. VERIFICATION
4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A.
4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices
DEFENSE SUPPLY CENTER COLUMBUS
Margin test method A. * Steps 1 through 3 may be performed at wafer level.
a. Burn-in test (method 1015 of MIL-STD-883).
b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter
c. A data retention stress shall be included as part of the screening procedure and shall consist of the following steps:
(1) Test condition C or D. The test circuit shall be maintained by the manufacturer under document revision level
(2) T
tests prior to burn-in are optional at the discretion of the manufacturer.
(1)
COLUMBUS, OHIO 43218-3990
MICROCIRCUIT DRAWING
control and shall be made available to the preparing or procuring activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1015 of MIL-STD-883.
A
At +25°C, program greater than 95 percent of the bit locations, including the slowest programming cell. The
remaining bits shall provide a worse case speed pattern.
= +125°C, minimum.
STANDARD
SIZE
A
REVISION LEVEL
B
SHEET
5962-87515
9