MCM69C433TQ15 Freescale, MCM69C433TQ15 Datasheet - Page 9

• Manufacturer Part Number: MCM69C433TQ15
• Manufacturer: Freescale

Specifications of MCM69C433TQ15

• Operating Temperature (max): 85C
• Package Type: TQFP
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Not Compliant

MOTOROLA FAST SRAM
match bit as defined by the mask register is ignored for this
operation. The operation of the MCM69C433 guarantees
that no more than one matching entry can exist in the table,
unless they were accidently loaded using fast–entry mode.
This must be avoided by the user, as the results of subse-
quent matches and deletes will be undefined.
Example: I/O Register 0 =
CHECK FOR VALUE
table via the control port. The contents of I/O registers 0 – 3
are concatenated, with bit 15 of register 3 as the most signifi-
cant bit, and bit 0 of register 0 as the least significant bit. The
bits that have a 0 in the corresponding bit of the global–mask
register are used to find a matching entry in the CAM table. If
such an entry is found, the last–match–successful bit of the
flag register is set. In addition, the matching entry is written to
I/O registers 0 – 3, with bit 15 of register 3 as the most signifi-
cant bit, and bit 0 of register 0 as the least significant bit
cleared. An interrupt is generated regardless of the result, if
enabled by bit 2 of the interrupt register, when the operation
has been completed. The operation of the MCM69C433
guarantees that no more than one matching entry can exist
in the table. If uninterrupted by match port activity, the check
for value instruction will finish in 16 clock cycles. NOTE: If
both the control and matching ports are utilized simulta-
neously, see the Simultaneous Port Operations section.
INITIALIZE TABLE
the initialize–table operation must be used to establish the
needed relationships and linkages between the entries in the
table before matching can proceed. Upon completion, this
operation sets the table–initialized bit in the flag register, and
generates an interrupt if enabled by bit 3 of the interrupt reg-
ister. It also sets the buffered–entry mode bit in the flag regis-
ter. This operation makes the programming model’s registers
read–only for up to 120 ms after the acknowledgment of the
op code write cycle.
FAST–ENTRY MODE
When the MCM69C433 is in this mode, insert–value opera-
tions bypass the entry queue and write new table entries
directly to the CAM table. The fast–entry mode can only be
entered while the entry queue is empty, as reflected by the
queue–empty flag being set (bit 4 of the flag register.) If this
operation is attempted while the entry queue is not empty,
the value FFFA 16 is written to the error code register, the
error–condition flag (bit 7) is set in the flag register, and an
This instruction checks for a matching value in the CAM
If no match is found, the last–match–successful bit is
If fast–entry mode has been used to load the CAM table,
This instruction is used to enter the fast–entry mode.
I/O Register 1 =
I/O Register 2 =
I/O Register 3 =
Concatenated value =
Global–Mask Register = C0000000FFFFFFFF 16
Of the high–order 32 bits, the rightmost 30 bits
are cared by the global–mask register. Therefore,
the MCM69C433 will delete an entry, if it exists,
which has a value of 3E55543A 16 in bits 61 – 32.
Freescale Semiconductor, Inc.
0000 16
543A 16
FE55 16
FE55543A00003020 16
3020 16
For More Information On This Product,
Go to: www.freescale.com
interrupt is generated if enabled by bit 4 of the interrupt
register.
tion must be executed before matching operations can
begin. The entry–mode bit and the table–initialized bit of the
flag register are cleared by this operation.
BUFFERED–ENTRY MODE
When the MCM69C433 is in this mode, insert–value and
delete–value operations utilize the entry queue. This mode
can be entered at any time. Table entries are available for
match operations immediately, without running the initialize–
table operation, if all entries are made in this mode. Note that
if both the buffered–entry and fast–entry modes have been
used to input data, none of the entries are available for
matching until the initialize–table operation is executed. Con-
flicting table and queue values are resolved in favor of the
latest entry in the queue. For example, if there is an entry in
the CAM, a corresponding delete–entry in the queue, and a
later insert–entry in the queue (all with the same match data),
the queued insert–entry will return a match value.
RETURN ENTRY COUNT
tries in the MCM69C433. The value is returned in I/O register
0, and reflects the sum of the number of valid entries in the
CAM table and the inserts in the entry queue.
SET GLOBAL–MASK REGISTER
forming matches. A 1 indicates that a bit should be ignored in
the match operation, while a 0 indicates that a bit should be
used in the match operation.
ters 0 – 3 are concatenated, with bit 15 of register 3 as the
most significant bit, and bit 0 of register 0 as the least signifi-
cant bit. The resulting 64–bit value is written to the global–
mask register.
quired values into the CAM table. Otherwise, the initialize–
table instruction must be executed if the global–mask
register is changed after data is loaded into the CAM.
SET ALMOST–FULL POINT
in the CAM table. The 14 low–order bits of I/O register 0 are
copied to the almost–full–point register. If an entry is added
to the MCM69C433 (via the insert–value operation) that
causes the valid–entry count to equal the almost–full point,
then bit 8 of the flag register is set, and an interrupt is gener-
ated if enabled by bit 5 of the interrupt register. The value of
the almost–full register can be changed dynamically during
match operations. For example, it could first be set to 8192 to
generate an interrupt when the table is half full. When that
point is reached, the register could be reprogrammed to
12,288 to provide warning that the table has become three–
quarters full. The almost–full interrupt is generated, if
enabled, based on the number of entries in the CAM table.
Entries in the queue are not included in the count.
If this mode is used to enter data, the initialize–table opera-
This instruction is used to enter the buffered–entry mode.
This operation is used to determine the number of valid en-
This operation is used to indicate the bits to be used in per-
When this operation is executed, the contents of I/O regis-
This operation should be executed before entering re-
This operation is used to define the “almost–full” condition
MCM69C433 SCM69C433
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