M368L6423FTNCB3 Samsung Semiconductor, M368L6423FTNCB3 Datasheet - Page 5

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M368L6423FTNCB3

Manufacturer Part Number
M368L6423FTNCB3
Description
Manufacturer
Samsung Semiconductor
Datasheet

Specifications of M368L6423FTNCB3

Main Category
DRAM Module
Sub-category
DDR SDRAM
Module Type
184UDIMM
Device Core Size
64b
Organization
64Mx64
Total Density
512MByte
Chip Density
256Mb
Access Time (max)
700ps
Maximum Clock Rate
333MHz
Operating Supply Voltage (typ)
2.5V
Operating Current
1.72A
Number Of Elements
16
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
184
Mounting
Socket
Lead Free Status / RoHS Status
Not Compliant
4.0 Pin Configuration (Front side/back side)
Note :
1. * : These pins are not used in this module.
2. Pins 44, 45, 47, 49, 51, 134, 135, 140, 142, 144 are used on x72 module ( M381~ ), and are not used on x64 module.
3. Pins 111, 158 are NC for 1row modules & used for 2row modules.
4. Pins 137, 138 are NC for x16 1Row module.
Note : VDDID defines relationship of VDD and VDDQ, and the default status of it is open (VDD=VDDQ)
128MB, 256MB, 512MB Unbuffered DIMM
5.0 Pin Description
A0 ~ A12
BA0 ~ BA1A
DQ0 ~ DQ63
DQS0 ~ DQS8
CK0,CK0 ~ CK2, CK2
CKE0, CKE1(for double banks) Clock enable input
CS0, CS1(for double banks)
RAS
CAS
WE
CB0 ~ CB7(for x72 module)
Pin
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
1
2
3
4
5
6
7
8
9
Pin Name
VDDQ
VDDQ
VDDQ
VREF
DQS0
DQS1
DQ10
DQ11
CKE0
DQ16
DQ17
DQS2
DQ18
DQ19
Front
DQ0
DQ1
DQ2
VDD
DQ3
DQ8
DQ9
VSS
VSS
CK1
CK1
VSS
VSS
NC
NC
A9
A7
Pin
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
KEY
Address input (Multiplexed)
Bank Select Address
Data input/output
Data Strobe input/output
Clock input
Chip select input
Row address strobe
Column address strobe
Write enable
Check bit(Data-in/data-out)
VDDQ
DQS3
DQS8
DQ32
DQS4
DQ35
DQ40
Front
DQ24
DQ25
DQ26
DQ27
DQ33
DQ34
VDD
VDD
VSS
VSS
CB0
CB1
CB2
VSS
CB3
VSS
BA1
BA0
A5
A4
A2
A1
A0
Function
Pin
68
62
63
64
65
66
67
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
VDDID
VDDQ
VDDQ
DQS5
DQS6
DQS7
Front
DQ41
DQ42
DQ43
DQ48
DQ49
DQ50
DQ51
DQ56
DQ57
DQ58
DQ59
*CS2
*CK2
*CK2
VDD
VDD
CAS
VSS
VSS
VSS
VSS
SDA
SCL
WE
NC
DM0 ~7,8(for ECC) Data - in mask
Pin Name
VDDSPD
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
Pin
SA0 ~ 2
93
94
95
96
97
98
99
VDDID
VDDQ
VREF
VDD
VSS
SDA
SCL
NC
VDDQ
VDDQ
VDDQ
DQ12
DQ13
DQ14
DQ15
CKE1
DQ20
DQ21
DQ22
DQ23
Back
*BA2
VSS
DQ4
DQ5
DM0
DQ6
DQ7
VSS
DM1
VDD
VSS
DM2
VDD
A12
A11
NC
NC
NC
A8
Power supply
(2.5V for DDR333, 2.6V for DDR400)
Power Supply for DQS
(2.5V for DDR333, 2.6V for DDR400)
Ground
Power supply for reference
Serial EEPROM Power/Supply ( 2.3V to 3.6V )
Serial data I/O
Serial clock
Address in EEPROM
VDD, VDDQ level detection
No connection
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
Pin
KEY
VDDQ
VDDQ
VDDQ
DQ28
DQ29
DQ30
DQ31
DQ36
DQ37
DQ38
DQ39
DQ44
Back
VSS
DM3
DM8
VDD
DM4
VSS
VSS
CB4
CB5
CK0
CK0
VSS
CB6
CB7
VSS
A10
Rev. 1.3 July 2005
A6
A3
Function
DDR SDRAM
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
Pin
VDDSPD
VDDQ
VDDQ
VDDQ
VDDQ
DQ45
DQ46
DQ47
DQ52
DQ53
DQ54
DQ55
DQ60
DQ61
DQ62
DQ63
Back
*CS3
RAS
DM5
*A13
VDD
DM6
DM7
CS0
CS1
VSS
VSS
SA0
SA1
SA2
NC

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