5962-8851805LA QP SEMICONDUCTOR, 5962-8851805LA Datasheet - Page 8

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5962-8851805LA

Manufacturer Part Number
5962-8851805LA
Description
Manufacturer
QP SEMICONDUCTOR
Datasheet

Specifications of 5962-8851805LA

Lead Free Status / RoHS Status
Supplier Unconfirmed
DSCC FORM 2234
APR 97
Mode
DEFENSE SUPPLY CENTER COLUMBUS
1/
2/
3/
4/
MICROCIRCUIT DRAWING
COLUMBUS, OHIO 43218-3990
X = don't care, but not to exceed V
During read operation, the output latches are loaded on a "0" to "1" transition of CP.
Pin Es must be LOW prior to the "0" to "1" transition on CP that loads the register.
Es must be HIGH prior to the "0" to "1" transition on CP that loads the register.
Read 1/ 2/ 3/
Output disable 1/ 4/
Output disable 1/
C ¯ L ¯ E ¯ A ¯ R ¯ 1/
P ¯ R ¯ E ¯ S ¯ E ¯ T ¯ 1/
STANDARD
Read or output disable
Other
FIGURE 3. Logic diagram
PP
FIGURE 2. Truth table.
= 13.0 V, maximum.
P ¯ G ¯ M ¯
CP
X
X
X
X
X
V ¯ F ¯ Y ¯
V
V
V
V
E
X
IL
IH
IL
IL
S
V
V
V
V
V
SIZE
IH
IH
IH
IL
IH
C ¯ L ¯ R ¯
V
A
PP
V
V
V
V
X
E ¯
E ¯
IL
IH
IL
IL
REVISION LEVEL
V
V
V
V
V
P ¯ S ¯
P ¯ S ¯
IH
IH
IH
IH
IL
Data out
High Z
High Z
Zeros
Ones
D
Outputs
SHEET
5962-88518
8

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