PI3VDP411LSZDE Pericom Semiconductor, PI3VDP411LSZDE Datasheet - Page 8

• Manufacturer Part Number: PI3VDP411LSZDE
• Manufacturer: Pericom Semiconductor

Specifications of PI3VDP411LSZDE

• Lead Free Status / RoHS Status: Compliant

TMDS Outputs
The level shifter's TMDS outputs are required to meet HDMI 1.3 specifi cations.
The HDMI 1.3 Specifi cation is assumed to be the correct reference in instances where this document confl icts
with the HDMI 1.3 specifi cation.
Table 6: Differential Output Characteristics for TMDS_OUT signals
Symbol
V
V
V
I
T
T
T
T
T
OFF
R
F
SKEW-INTRA
SKEW-INTER
JIT
H
L
SWING
08-0294
Parameter
Single-ended
high level output
voltage
Single-ended
low level output
voltage
Single-ended
output swing
voltage
Single-ended
current in high-Z
state
Rise time
Fall time
Intra-pair
differential skew
Inter-pair lane-
to-lane output
skew
Jitter added to
TMDS signals
Min
VDD-10mV
VDD-600mV
450mV
125ps
125ps
Nom
VDD
VDD-500mV
500mV
8
digital video input to a DVI/HDMI transmitter
Max
VDD+10mV
VDD-400mV
600mV
50
0.4Tbit
0.4Tbit
30
100
25
Digital Video Level Shifter from AC coupled
Units Comments
V
V
V
μA
ps
ps
ps
ps
ps
VDD is the DC termination
voltage in the HDMI or DVI
Sink. VDD is nominally 3.3V
The open-drain output pulls
down from VDD.
Swing down from TMDS
termination voltage (3.3V ±
10%)
Measured with TMDS out-
puts pulled up to VDD Max
_(3.6V) through 50Ω resistors.
Max Rise/Fall time @2.7Gbps
= 148ps. 125ps = 148-15%
Max Rise/Fall time @2.7Gbps
= 148ps. 125ps = 148-15%
This differential skew bud-
get is in addition to the skew
presented between D+ and
D- paired input pins. HDMI
revision 1.3 source allowable
intra-pair skew is 0.15Tbit.
This lane-to-lane skew budget
is in addition to skew between
differential input pairs
Jitter budget for TMDS
signals as they pass through
the level shifter. 25ps =
0.056 Tbit at 2.25 Gb/s
PI3VDP411LS
PS8913D
11/05/08