RG82845 S L5YQ Intel, RG82845 S L5YQ Datasheet - Page 75

• Manufacturer Part Number: RG82845 S L5YQ
• Manufacturer: Intel

Specifications of RG82845 S L5YQ

• Lead Free Status / RoHS Status: Not Compliant

3.5.35
Intel
®
82845 MCH for SDR Datasheet
R
ERRSTS—Error Status Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
This register is used to report various error conditions via the hub interface messages to ICH2. An
SERR, SMI, or SCI error message may be generated via the hub interface on a zero to one
transition of any of these flags when enabled in the PCICMD/ERRCMD, SMICMD, or SCICMD
registers, respectively. These bits are set, regardless of whether or not the SERR is enabled and
generated.
15:10
Bit
8:7
9
6
5
4
3
2
1
Reserved.
LOCK to non-DRAM Memory Flag (LCKF).
0 = Software must write a 1 to clear this status bit.
1 = Indicates that a host initiated LOCK cycle targeting non-DRAM memory space occurred.
Reserved.
SERR on Hub Interface Target Abort (TAHLA).
0 = Software must write a 1 to clear this status bit.
1 = MCH detected that a MCH-originated hub interface cycle was terminated with a Target Abort
MCH Detects Unimplemented Hub Interface Special Cycle (HIAUSC).
0 = Software must write a 1 to clear this status bit.
1 = MCH detected an Unimplemented Special Cycle on the hub interface.
AGP Access Outside of Graphics Aperture Flag (OOGF).
0 = Software must write a 1 to clear this status bit.
1 = Indicates that an AGP access occurred to an address that is outside of the graphics aperture
Invalid AGP Access Flag (IAAF).
0 = Software must write a 1 to clear this status bit.
1 = Indicates that an AGP access was attempted outside of the graphics aperture and either to
Invalid Graphics Aperture Translation Table Entry (ITTEF).
0 = Software must write a 1 to clear this status bit.
1 = Indicates that an invalid translation table entry was returned in response to an AGP access
Multiple-bit DRAM ECC Error Flag (DMERR).
0 = After software completes the error processing, a value of 1 is written to this bit field to set the
1 = A memory read data transfer had an uncorrectable multiple-bit error. When this bit is set, the
completion packet or special cycle.
range.
the 640 KB – 1 MB range or above the top of memory.
to the graphics aperture.
value back to 0 and unlock the error logging mechanism.
address and device number that caused the error are logged in the EAP Register. Software
uses bits [1:0] to detect whether the logged error address is for Single or Multiple-bit error.
C8–C9h
0000h
R/WC
16 bits
Description
Register Description
75