NH82801DB Intel Corporation, NH82801DB Datasheet

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NH82801DB

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NH82801DB
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Intel 82801DB I/O Controller Hub (ICH4), Pb-Free SLI
Manufacturer
Intel Corporation
Datasheet

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®
Intel
82801DB I/O Controller
Hub 4 (ICH4)
Datasheet
May 2002
Document Number: 290744-001

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NH82801DB Summary of contents

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Intel 82801DB I/O Controller Hub 4 (ICH4) Datasheet May 2002 Document Number: 290744-001 ...

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... Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel's website at http://www.intel.com. Intel, Intel SpeedStep, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. ...

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Intel 82801DB ICH4 Features PCI Bus Interface — Supports PCI Revision 2.2 Specification at 33 MHz — 133 MB/sec maximum throughput — Supports up to six master devices on PCI — One PCI REQ/GNT pair can be given higher ...

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System Configuration 4 Processor Host Controller AGP USB (Supports 6 USB 2.0 ports) IDE-Primary IDE-Secondary ® Intel AC’97 Codec(s) 82801DB ICH4 LAN Connect GPIO Firmware Hub(s) LPC Interface Firmware Hubs (1-8) Super I/O Super I/O Othe ASIC Other ASICs r ...

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Contents 1 Introduction 1.1 About This Datasheet ....................................................................................27 1.2 Overview ........................................................................................................30 2 Signal Description 2.1 Hub Interface to Host Controller ....................................................................39 2.2 Link to LAN Connect ......................................................................................39 2.3 EEPROM Interface ........................................................................................40 2.4 Firmware Hub Interface .................................................................................40 2.5 PCI Interface ..................................................................................................40 ...

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LAN Controller (B1:D8:F0)............................................................................. 72 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.3 LPC Bridge (w/ System and Management Functions) (D31:F0).................... 86 5.3.1 5.4 DMA Operation (D31:F0) ............................................................................... 92 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.5 PCI DMA........................................................................................................ 96 5.5.1 5.5.2 5.5.3 ...

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Real Time Clock (D31:F0) ...........................................................................127 5.10.1 Update Cycles.................................................................................127 5.10.2 Interrupts.........................................................................................128 5.10.3 Lockable RAM Ranges ...................................................................128 5.10.4 Century Rollover .............................................................................128 5.10.5 Clearing Battery-Backed RTC RAM................................................128 5.11 Processor Interface (D31:F0).......................................................................130 5.11.1 Processor Interface Signals ............................................................130 5.11.2 Dual-Processor Designs .................................................................132 5.11.3 ...

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USB 2.0 Enhanced Host Controller DMA ....................................... 196 5.17.4 Data Encoding and Bit Stuffing....................................................... 199 5.17.5 Packet Formats............................................................................... 199 5.17.6 USB EHCI Interrupts and Error Conditions..................................... 200 5.17.7 USB EHCI Power Management...................................................... 201 5.17.8 Interaction with Classic Host Controllers ...

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SVID — Subsystem Vendor ID (LAN Controller—B1:D8:F0) .........257 7.1.14 SID — Subsystem ID (LAN Controller—B1:D8:F0) ........................257 7.1.15 CAP_PTR — Capabilities Pointer (LAN Controller—B1:D8:F0) .....258 7.1.16 INT_LN — Interrupt Line Register (LAN Controller—B1:D8:F0).....258 7.1.17 INT_PN — Interrupt Pin Register (LAN ...

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SMLT—Secondary Master Latency Timer Register 8.1.14 IOBASE—I/O Base Register (HUB-PCI—D30:F0) ......................... 281 8.1.15 IOLIM—I/O Limit Register (HUB-PCI—D30:F0) ............................. 281 8.1.16 SECSTS—Secondary Status Register (HUB-PCI—D30:F0).......... 282 8.1.17 MEMBASE—Memory Base Register (HUB-PCI—D30:F0) ............ 283 8.1.18 MEMLIM—Memory Limit Register (HUB-PCI—D30:F0) ................ 283 ...

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D31_ERR_STS—Device 31 Error Status Register 9.1.21 PCI_DMA_CFG—PCI DMA Configuration (LPC I/F—D31:F0) ......301 9.1.22 GEN_CNTL — General Control Register (LPC I/F — D31:F0) ......302 9.1.23 GEN_STA—General Status Register (LPC I/F—D31:F0) ..............304 9.1.24 BACK_CNTL—Backed Up Control Register 9.1.25 RTC_CONF—RTC Configuration Register ...

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ELCR2—Slave Controller Edge/Level Triggered Register ............. 330 9.5 Advanced Interrupt Controller (APIC) .......................................................... 331 9.5.1 9.5.2 9.5.3 9.5.4 9.5.5 9.5.6 9.5.7 9.5.8 9.5.9 9.5.10 Redirection Table............................................................................ 335 9.6 Real Time Clock Registers .......................................................................... 337 9.6.1 9.6.2 9.7 Processor Interface ...

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STS — Device Status Register (IDE—D31:F1) ..............................385 10.1.5 REVID—Revision ID Register (IDE—D31:F1) ................................385 10.1.6 PI — Programming Interface Register (IDE—D31:F1) ...................386 10.1.7 SCC — Sub Class Code Register (IDE—D31:F1)..........................386 10.1.8 BCC — Base Class Code Register (IDE—D31:F1) ........................386 10.1.9 ...

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USB_LEGKEY—USB Legacy Keyboard/Mouse Control Register 11.1.17 USB_RES—USB Resume Enable Register 11.2 USB I/O Registers ....................................................................................... 407 11.2.1 USBCMD—USB Command Register ............................................. 408 11.2.2 USBSTS—USB Status Register ..................................................... 411 11.2.3 USBINTR—Interrupt Enable Register............................................. 412 11.2.4 FRNUM—Frame Number Register................................................. 412 11.2.5 ...

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LEG_EXT_CAP—USB EHCI Legacy Support Extended Capability 12.1.27 LEG_EXT_CS—USB EHCI Legacy Support Extended Control / 12.1.28 SPECIAL_SMI—Intel Specific USB EHCI SMI Register 12.1.29 ACCESS_CNTL—Access Control Register 12.1.30 HS_Ref_V—USB HS Reference Voltage Register 12.2 Memory-Mapped I/O Registers....................................................................432 12.2.1 Host Controller Capability ...

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AC ’97 Audio Controller Registers (D31:F5) 14.1 AC ’97 Audio PCI Configuration Space (D31:F5) ........................................ 467 14.1.1 VID—Vendor Identification Register (Audio—D31:F5) ................... 468 14.1.2 DID—Device Identification Register (Audio—D31:F5).................... 468 14.1.3 PCICMD—PCI Command Register (Audio—D31:F5) .................... 469 14.1.4 PCISTS—PCI Device ...

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SCC—Sub Class Code Register (Modem—D31:F6)......................496 15.1.8 BCC—Base Class Code Register (Modem—D31:F6) ....................496 15.1.9 HEDT—Header Type Register (Modem—D31:F6).........................496 15.1.10 MMBAR—Modem Mixer Base Address Register 15.1.11 MBAR—Modem Base Address Register (Modem—D31:F6) .........497 15.1.12 SVID—Subsystem Vendor ID (Modem—D31:F6) ..........................498 15.1.13 SID—Subsystem ID ...

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Figures n System Configuration ...................................................................................... 4 2-1 Intel 2-2 Example External RTC Circuit ....................................................................... 54 2-3 Example V5REF Sequencing Circuit ............................................................. 55 4-1 Conceptual System Clock Diagram ............................................................... 66 5-1 Primary Device Status Register Error Reporting Logic.................................. 69 5-2 Secondary ...

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G3 (Mechanical Off Timings..............................................................546 17- Timing ..................................................................................546 17- Timings ................................................................................547 17- Timings................................................................................547 17-23 AC ’97 Data Input and Output Timings ........................................................548 18-1 ...

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Tables 1-1 Industry Specifications................................................................................... 27 1-2 PCI Devices and Functions ........................................................................... 30 2-1 Hub Interface Signals .................................................................................... 39 2-2 LAN Connect Interface Signals...................................................................... 39 2-3 EEPROM Interface Signals ........................................................................... 40 2-4 Firmware Hub Interface Signals .................................................................... 40 2-5 PCI Interface ...

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Short Message.............................................................................................117 5-22 APIC Bus Status Cycle Definition ................................................................118 5-23 Lowest Priority Message (Without Focus Processor) ..................................119 5-24 Remote Read Message ...............................................................................120 5-25 Interrupt Message Address Format .............................................................123 5-26 Interrupt Message Data Format ...................................................................124 5-27 Stop Frame Explanation ..............................................................................125 ...

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SOF Packet ................................................................................................. 188 5-73 Data Packet Format..................................................................................... 188 5-74 Bits Maintained in Low Power States .......................................................... 192 5-75 USB Legacy Keyboard State Transitions .................................................... 194 5-76 UHCI vs. EHCI............................................................................................. 195 5-77 Debug Port Behavior ................................................................................... 206 5-78 Quick ...

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PCI Configuration Map (PM—D31:F0) ........................................................345 9-9 APM Register Map.......................................................................................352 9-10 ACPI and Legacy I/O Register Map.............................................................353 9-11 TCO I/O Register Map .................................................................................371 9-12 Registers to Control GPIO ...........................................................................378 10-1 PCI Configuration Register Address Map (IDE—D31:F1) ...........................383 10-2 Bus Master ...

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XOR Chain 4-2 ............................................................................................ 557 19-8 XOR Chain 6................................................................................................ 557 19-9 LONG XOR Chain ....................................................................................... 558 A-1 Intel A-2 Intel A-3 Intel 24 ® ICH4 PCI Configuration Registers ..................................................... 561 ® ICH4 Fixed I/O Registers ................................................................... 571 ® ICH4 ...

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Intel 82801DB ICH4 Datasheet This page is intentionally left blank 25 ...

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Revision History Revision -001 Initial release 26 Description ® Intel 82801DB ICH4 Datasheet Date May 2002 ...

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Introduction 1.1 About This Datasheet This datasheet is intended for Original Equipment Manufacturers and BIOS vendors creating ICH4-based products. This datasheet assumes a working knowledge of the vocabulary and principles of USB, IDE, AC ’97, SMBus, PCI, ACPI and LPC. ...

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Introduction Chapter 5. Functional Description Chapter 5 provides a detailed description of the functions in the ICH4. All PCI buses, devices, and functions in this datasheet are abbreviated using the following nomenclature; Bus:Device:Function. This datasheet abbreviates buses as B0 and ...

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Chapter 16. Pinout Definition Chapter 16 provides a table of each signal and its ball assignment in the 421 BGA package. Chapter 17. Electrical Characteristics Chapter 17 provides all AC and DC characteristics including detailed timing diagrams. Chapter 18. Package ...

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Introduction 1.2 Overview The ICH4 provides extensive I/O support. Functions and capabilities include: • PCI Local Bus Specification, Revision 2.2-compliant with support for 33 MHz PCI operations. • PCI slots ( supports Req/Gnt pairs) • ACPI Power ...

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The following sub-sections provide an overview of the ICH4 capabilities. Hub Architecture As I/O speeds increase, the demand placed on the PCI bus by the I/O bridge has become significant. With AC ’97, USB 2.0, and Ultra ATA/100, coupled with ...

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Introduction Compatibility Modules (DMA Controller, Timer/Counters, Interrupt Controller) The DMA controller incorporates the logic of two 82C37 DMA controllers, with seven independently programmable channels. Channels 0–3 are hardwired to 8-bit, count-by-byte transfers, and channels 5–7 are hardwired to 16-bit, count-by-word ...

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LAN Controller The ICH4’s integrated LAN controller includes a 32-bit PCI controller that provides enhanced scatter-gather bus mastering capabilities and enables the LAN controller to perform high-speed data transfers over the PCI bus. Its bus master capabilities enable the component ...

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Introduction Manageability The ICH4 integrates several functions designed to manage the system and lower the total cost of ownership (TC0) of the system. These system management functions are designed to report errors, diagnose the system, and recover from system lockups ...

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AC ’97 2.3 Controller The Audio Codec ’97, Revision 2.3 specification defines a digital interface that can be used to attach an audio codec (AC), a modem codec (MC), an audio/modem codec (AMC combination of ACs and MC. ...

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Introduction 36 This page is intentionally left blank. ® Intel 82801DB ICH4 Datasheet ...

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Signal Description This section provides a detailed description of each signal. The signals are arranged in functional groups according to their associated interface. The “#” symbol at the end of the signal name indicates that the active, or asserted state ...

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Signal Description ® Figure 2-1. Intel ICH4 Interface Signals Block Diagram AD[31:0] C/BE[3:0]# DEVSEL# FRAME# TRDY# STOP# PERR# REQ[4:0]# REQ5# / REQB# / GPIO1 REQA# / GPIO0 GNT[4:0]# GNT5# / GNTB# / GPIO17 GNTA# / GPIO[16] PCICLK PCIRST# PLOCK# SERR# ...

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Hub Interface to Host Controller Table 2-1. Hub Interface Signals Name HI[11:0] HI_STB / HI_STBS HI_STB# / HI_STBF HICOMP HI_VSWING 2.2 Link to LAN Connect Table 2-2. LAN Connect Interface Signals Name LAN_CLK LAN_RXD[2:0] LAN_TXD[2:0] LAN_RSTSYNC ® Intel 82801DB ...

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Signal Description 2.3 EEPROM Interface Table 2-3. EEPROM Interface Signals Name EE_SHCLK EE_DIN EE_DOUT EE_CS 2.4 Firmware Hub Interface Table 2-4. Firmware Hub Interface Signals Name FWH[3:0] / LAD[3:0] FWH[4] / LFRAME# 2.5 PCI Interface Table 2-5. PCI Interface Signals ...

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Table 2-5. PCI Interface Signals (Sheet Name DEVSEL# FRAME# IRDY# TRDY# STOP# PAR PERR# REQ[0:4]# REQ[5]# / REQ[B]# / GPIO[1] ® Intel 82801DB ICH4 Datasheet Type Device Select: The ICH4 asserts DEVSEL# to claim a PCI transaction. ...

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Signal Description Table 2-5. PCI Interface Signals (Sheet Name GNT[0:4]# GNT[5]# / GNT[B]# / GPIO[17]# PCICLK PCIRST# PLOCK# SERR# PME# REQ[A]# / GPIO[0] REQ[B]# / REQ[5]# / GPIO[1] GNT[A]# / GPIO[16] GNT[B]# / GNT[5]# / GPIO[17] 42 ...

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IDE Interface Table 2-6. IDE Interface Signals Name PDCS1#, SDCS1# PDCS3#, SDCS3# PDA[2:0], SDA[2:0] PDD[15:0], SDD[15:0] PDDREQ, SDDREQ PDDACK#, SDDACK# PDIOR# / (PDWSTB / PRDMARDY#) SDIOR# / (SDWSTB / SRDMARDY#) PDIOW# / (PDSTOP) SDIOW# / (SDSTOP) PIORDY / (PDRSTB ...

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Signal Description 2.7 LPC Interface Table 2-7. LPC Interface Signals Name LAD[3:0] / FWH[3:0] LFRAME# / FWH[4] LDRQ[1:0]# 2.8 Interrupt Interface Table 2-8. Interrupt Signals Name SERIRQ PIRQ[D:A]# PIRQ[H:E]# / GPIO[5:2] IRQ[14:15] APICCLK APICD[1:0] 44 Type LPC Multiplexed Command, Address, ...

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USB Interface Table 2-9. USB Interface Signals Name USBP0P, USBP0N, USBP1P, USBP1N USBP2P, USBP2N, USBP3P, USBP3N USBP4P, USBP4N, USBP5P, USBP5N OC[5:0]# USBRBIAS USBRBIAS# ® Intel 82801DB ICH4 Datasheet Type Universal Serial Bus Port 1:0 Differential: These differential pairs are ...

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Signal Description 2.10 Power Management Interface Table 2-10. Power Management Interface Signals Name THRM# THRMTRIP# SLP_S3# SLP_S4# SLP_S5# PWROK PWRBTN# RI# SYS_RESET# RSMRST# LAN_RST# SUS_STAT# / LPCPD# SUSCLK VRMPWRGD 46 Type Thermal Alarm: This is an active low signal generated ...

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Processor Interface Table 2-11. Processor Interface Signals (Sheet Name A20M# CPUSLP# FERR# IGNNE# INIT# INTR NMI SMI# STPCLK# ® Intel 82801DB ICH4 Datasheet Type Mask A20: A20M# will go active based on either setting the appropriate ...

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Signal Description Table 2-11. Processor Interface Signals (Sheet Name RCIN# A20GATE CPUPWRGD 2.12 SMBus Interface Table 2-12. SM Bus Interface Signals Name SMBDATA SMBCLK SMBALERT#/ GPIO[11] 2.13 System Management Interface Table 2-13. System Management Interface Signals Name ...

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Real Time Clock Interface Table 2-14. Real Time Clock Interface Name RTCX1 Special RTCX2 Special 2.15 Other Clocks Table 2-15. Other Clocks Name CLK14 CLK48 CLK66 2.16 Miscellaneous Signals Table 2-16. Miscellaneous Signals Name SPKR RTCRST# TP[0] ® Intel ...

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Signal Description 2.17 AC-Link Table 2-17. AC-Link Signals Name AC_RST# AC_SYNC AC_BIT_CLK AC_SDOUT AC_SDIN[2:0] NOTE: An integrated pull-down resistor on AC_BIT_CLK is enabled when either: - The ACLINK Shutoff bit in the AC ’97 Global Control Register (See - Both ...

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General Purpose I/O Table 2-18. General Purpose I/O Signals Name GPIO[47:44] GPIO[43:38] GPIO[37:32] GPIO[31:29] GPIO[28:27] GPIO[26] GPIO[25] GPIO[24] GPIO[23] GPIO[22] GPIO[21] GPIO[20] GPIO[19] GPIO[18] GPIO[17:16] GPIO[15:14] GPIO[13:12] GPIO[11] GPIO[10:9] GPIO[8] GPIO[7] GPIO[6] GPIO[5:2] GPIO[1:0] NOTE: Main power well GPIO ...

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Signal Description 2.19 Power and Ground Table 2-19. Power and Ground Signals Name Vcc3_3 Vcc1_5 VccHI V5REF HIREF VccSus3_3 VccSus1_5 V5REF_Sus VccRTC VccPLL VBIAS V_CPU_IO Vss 52 Description 3.3 V supply for core well I/O buffers. This power may be ...

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Pin Straps 2.20.1 Functional Straps The following signals are used for static configuration. They are sampled at the rising edge of PWROK to select configurations, and then revert later to their normal usage. To invoke the associated mode, the ...

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Signal Description 2.20.2 External RTC Circuitry To reduce RTC well power consumption, the ICH4 implements an internal oscillator circuit that is sensitive to step voltage changes in VccRTC and VBIAS. the circuitry required to condition these voltages to ensure correct ...

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Figure 2-3. Example V5REF Sequencing Circuit Vcc Supply To System 2.20.4 Test Signals 2.20.4.1 Test Mode Selection When PWROK is active (high) for at least 76 PCI clocks, driving RTCRST# active (low) for a number of PCI clocks (33 MHz) ...

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Signal Description 56 This page is intentionally left blank. ® Intel 82801DB ICH4 Datasheet ...

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Intel ICH4 Power Planes and Pin States This chapter describes the describes the system power planes for the ICH4. In addition, the ICH4 power planes and reset pin states for various signals are presented. 3.1 Power Planes ® Table ...

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Intel ICH4 Power Planes and Pin States 3.2 Integrated Pull-Ups and Pull-Downs Table 3-2. Integrated Pull-Up and Pull-Down Resistors Signal AC_BITCLK AC_RST# AC_SDIN[2:0] AC_SDOUT AC_SYNC EE_DIN EE_DOUT GNT[B:A]# / GNT[5]# / GPIO[17:16] LAD[3:0]# / FWH[3:0]# LDRQ[1:0] LAN_RXD[2:0] LAN_CLK PME# ...

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Output and I/O Signals Planes and States Table 3-4 shows the power plane associated with the output and I/O signals, as well as the state at various times. Within the table, the following terms are used: “High-Z” “High” “Low” ...

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Intel ICH4 Power Planes and Pin States Table 3-4. Power Plane and States for Output and I/O Signal (Sheet Signal Name LAD[3:0] LFRAME# EE_CS EE_DOUT EE_SHCLK LAN_RSTSYNC LAN_TXD[2:0] PDA[2:0], SDA[2:0] PDCS1#, PDCS3# PDD[15:8], SDD[15:8], PDD[6:0], SDD[6:0] ...

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Table 3-4. Power Plane and States for Output and I/O Signal (Sheet Signal Name SLP_S3# SLP_S4# SLP_S5# SUS_STAT# SUSCLK A20M# CPUPWRGD CPUSLP# IGNNE# INIT# INTR NMI SMI# STPCLK# SMBCLK, SMBDATA SMLINK[1:0] SPKR AC_RST# AC_SDOUT AC_SYNC ® Intel ...

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Intel ICH4 Power Planes and Pin States Table 3-4. Power Plane and States for Output and I/O Signal (Sheet Signal Name GPIO[18] GPIO[19:20] GPIO[21] GPIO[22] GPIO[23] GPIO[24] GPIO[25] GPIO[27:28] GPIO[32:43] NOTES: 1. ICH4 sets these signals ...

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Power Planes for Input Signals Table 3-5 shows the power plane associated with each input signal, as well as what device drives the signal at various times. Valid states include: High Low Static: Will be high or low, but ...

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Intel ICH4 Power Planes and Pin States Table 3-5. Power Plane for Input Signals (Sheet Signal Name LAN_RST# RSMRST# RTCRST# SDDREQ SERR# SIORDY SMBALERT# SYS_RESET# THRM# THRMTRIP# USBRBIAS# VRMPWRGD 64 Power Well Driver During Reset Resume ...

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Intel ICH4 and System Clock Domains Table 4-1 shows the system clock domains. various system components, including the clock generator in both desktop and mobile systems. For complete details of the system clocking solution refer to the system’s clock ...

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Intel ICH4 and System Clock Domains Figure 4-1. Conceptual System Clock Diagram Intel ICH4 32 kHz XTAL 66 66 MHz 33 MHz Clock APIC CLK Gen. 14.31818 MHz ® 48 MHz 12.288 MHz AC ’97 Codec(s) 50 MHz LAN ...

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Functional Description This chapter describes the functions and interfaces of the ICH4. 5.1 Hub Interface to PCI Bridge (D30:F0) The hub interface to PCI Bridge resides in PCI Device 30, Function 0 on bus #0. This portion of the ICH4 ...

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Functional Description Note: If the processor issues a locked cycle to a resource that is too slow (e.g., PCI), the ICH4 will not allow upstream requests to be performed until the cycle completion. This may be critical for isochronous buses ...

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Figure 5-1. Primary Device Status Register Error Reporting Logic D30:F0 BRIDGE_CNT [Parity Error Response Enable] PCI Address Parity Error Delayed Transaction Timeout Received Target Abort Figure 5-2. Secondary Status Register Error Reporting Logic PCI Delayed Transaction Timeout D31:F0 D31_ERR_CFG [SERR_DTT_EN] ...

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Functional Description Figure 5-3. NMI# Generation Logic IOCHK From SERIRQ Logic [IOCHK_NMI_EN] NMI_SC [PCI_SERR_EN] D30:F0 SECSTS [SSE] D30:F0 PDSTS [SSE] Hub Interface Parity Error Detected D30:F0 CMD [Parity Error Response] PCI Parity Error detected during AC'97, IDE or USB Master ...

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Standard PCI Bus Configuration Mechanism The PCI Bus defines a slot based “configuration space” that allows each device to contain up to eight functions with each function containing up to 256, 8-bit configuration registers. The PCI specification defines two ...

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Functional Description 5.1.7 PCI Dual Address Cycle (DAC) Support The ICH4 supports Dual Address Cycle (DAC) format on PCI for cycles from PCI initiators to main memory. This allows PCI masters to generate an address bits. The ...

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LAN Controller Architectural Overview Figure 5 high level block diagram of the ICH4 integrated LAN controller divided into four main subsystems: a Parallel subsystem, a FIFO subsystem and the Carrier-Sense Multiple Access with Collision Detect ...

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Functional Description concurrently. Control is switched between the two units according to the microcode instruction flow. The independence of the Receive and Command units in the micromachine allows the LAN controller to execute commands and receive incoming frames simultaneously, with ...

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LAN Controller PCI Bus Interface As a Fast Ethernet controller, the role of the ICH4 integrated LAN controller is to access transmitted data or deposit received data. The LAN controller bus master device, will initiate memory cycles ...

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Functional Description Write Accesses: The processor, as the initiator, drives the address lines AD[31:0], the command and byte enable lines C/BE[3:0]# and the control lines IRDY# and FRAME#. It also provides the LAN controller with valid data on each data ...

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Bus Master Operation As a PCI Bus Master, the ICH4 integrated LAN controller initiates memory cycles to fetch data for transmission or deposit received data and for accessing the memory resident control structures. The LAN controller performs zero wait-state ...

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Functional Description Cycle Completion: The LAN controller completes (terminates) its initiated memory burst cycles in the following cases: • Normal Completion: All transaction data has been transferred to or from the target device (for example, host main memory). • Backoff: ...

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If any one of the above conditions does not hold, the LAN controller will use the MW command MWI cycle has started and one of the conditions is no longer valid (for example, the data space in the ...

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Functional Description 5.2.2.3 PCI Power Management Enhanced support for the power management standard, PCI Local Bus Specification, Revision 2.2, is provided in the ICH4 integrated LAN controller. The LAN controller supports a large set of wake-up packets and the capability ...

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D1 Power State In order for a device to meet the D1 power state requirements, as specified in the Advanced Configuration and Power Interface (ACPI) Specification, Revision 2.0, it must not allow bus transmission or interrupts; however, bus reception ...

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Functional Description 5.2.2.5 Wake-Up Events There are two types of wake-up events: “Interesting” Packets and Link Status Change. These two events are detailed below. Note: If the Wake on LAN bit in the EEPROM is not set, wake-up events are ...

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Wake on LAN* (Preboot Wake-Up) The LAN controller enters Wake on LAN mode after reset if the Wake on LAN bit in the EEPROM is set. At this point, the LAN controller is in the D0u state. When the ...

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Functional Description 5.2.4 CSMA/CD Unit The ICH4 integrated LAN controller CSMA/CD unit implements both the IEEE 802.3 Ethernet 10 Mbps and IEEE 802.3u Fast Ethernet 100 Mbps standards. It performs all the CSMA/CD protocol functions (e.g., transmission, reception, collision handling, ...

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VLAN Support The LAN controller supports the IEEE 802.1 standard VLAN. All VLAN flows will be implemented by software. The LAN controller supports the reception of long frames, specifically frames longer than 1518 bytes, including the CRC, if software ...

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Functional Description 5.3 LPC Bridge (w/ System and Management Functions) (D31:F0) The LPC Bridge function of the ICH4 resides in PCI Device 31:Function 0. In addition to the LPC bridge function, D31:F0 contains other functional units including DMA, Interrupt controllers, ...

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LPC Cycle Types The ICH4 implements all of the cycle types described in the Low Pin Count Interface Specification, Revision 1.0. Table 5-2. LPC Cycle Types Supported Cycle Type Memory Read Memory Write I/O Read I/O Write DMA Read ...

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Functional Description 5.3.1.3 Cycle Type / Direction (CYCTYPE + DIR) The ICH4 will always drive bit 0 of this field to 0. Peripherals running bus master cycles must also drive bit Table 5-4 Table 5-4. Cycle Type ...

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SYNC Time-Out There are several error cases that can occur on the LPC interface. case and the ICH4 response. ® Table 5-7. Intel ICH4 Response to Sync Failures ® Intel ICH4 starts a Memory, I/O, or DMA cycle, but ...

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Functional Description 5.3.1.8 LFRAME# Usage Start of Cycle For Memory, I/O, and DMA cycles, the ICH4 asserts LFRAME# for 1 clock at the beginning of the cycle (Figure 5-7). During that clock, the ICH4 drives LAD[3:0] with the proper START ...

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I/O Cycles For I/O cycles targeting registers specified in the ICH4’s decode ranges, the ICH4 performs I/O cycles as defined in the LPC specification. These will be 8-bit transfers. If the processor attempts a 16-bit or 32-bit transfer, the ...

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Functional Description 5.4 DMA Operation (D31:F0) The ICH4 supports two types of DMA: LPC, and PC/PCI. DMA via LPC is similar to ISA DMA. LPC DMA and PC/PCI DMA use the ICH4’s DMA controller. The DMA controller has registers that ...

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Channel Priority For priority resolution, the DMA consists of two logical channel groups: channels 0–3 and channels 4–7. Each group may be in either fixed or rotate mode, as determined by the DMA Command Register. DMA I/O slaves normally ...

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Functional Description 5.4.3 Summary of DMA Transfer Sizes Table 5-8 lists each of the DMA device transfer sizes. The column labeled “Current Byte/Word Count Register” indicates that the register contents represents either the number of bytes to transfer or the ...

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Software Commands There are three additional special software commands that the DMA controller can execute. The three software commands are: • Clear Byte Pointer Flip-Flop • Master Clear • Clear Mask Register They do not depend on any specific ...

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Functional Description 5.5 PCI DMA ICH4 provides support for the PC/PCI DMA protocol. PC/PCI DMA uses dedicated REQUEST and GRANT signals to permit PCI devices to request transfers associated with specific DMA channels. Upon receiving a request and getting control ...

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All PCI DMA expansion agents must use the channel passing protocol described above. They must also work as follows: • PCI DMA expansion agent has more than one request active, it must resend the request serial protocol after ...

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Functional Description The I/O portion of the DMA cycle generates a PCI I/O cycle to one of four I/O addresses (Table 5-10). Note that these cycles must be qualified by an active GNT# signal to the requesting device. Table 5-10. ...

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DMA Cycle Termination DMA cycles are terminated when a terminal count is reached in the DMA controller and the channel is not in autoinitialize mode, or when the PC/PCI device deasserts its request. The PC/PCI device must follow explicit ...

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Functional Description 5.5.9 Abandoning DMA Requests DMA Requests can be deasserted in two fashions: on error conditions by sending an LDRQ# message with the “ACT” bit set normally through a SYNC field during the DMA transfer. This ...

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Terminal Count Terminal count is communicated through LAD[3] on the same clock that DMA channel is communicated on LAD[2:0]. This field is the CHANNEL field. Terminal count indicates the last byte of transfer, based upon the size of the ...

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Functional Description The peripheral must not assume that the next START indication from the ICH4 is another grant to the peripheral if it had indicated a SYNC value of 1001b single mode DMA device, the 8237 will re-arbitrate ...

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Timers (D31:F0) The ICH4 contains three counters which have fixed uses. All registers and functions associated with the 8254 timers are in the core well. The 8254 unit is clocked by a 14.31818 MHz clock. Counter 0, System ...

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Functional Description If a counter is programmed to read/write two-byte counts, the following precaution applies: A program must not transfer control between writing the first and second byte to another routine which also writes into that same counter. Otherwise, the ...

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Counter Latch Command The Counter Latch Command, written to port 43h, latches the count of a specific counter at the time the command is received. This command is used to ensure that the count read from the counter is ...

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Functional Description 5.7 8259 Interrupt Controllers (PIC) (D31:F0) The ICH4 incorporates the functionality of two 8259 interrupt controllers that provide system interrupts for the ISA compatible interrupts. These interrupts are: system timer, keyboard controller, serial ports, parallel ports, floppy disk, ...

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Interrupt Handling 5.7.1.1 Generating Interrupts The PIC interrupt sequence involves three bits, from the IRR, ISR, and IMR, for each interrupt level. These bits are used to determine the interrupt vector returned, and status of any other pending interrupts. ...

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Functional Description 5.7.1.3 Hardware/Software Interrupt Sequence 1. One or more of the Interrupt Request lines (IRQ) are raised high in edge mode, or seen high in level mode, setting the corresponding IRR bit. 2. The PIC sends INTR active to ...

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ICW2 The second write in the sequence (ICW2) is programmed to provide bits [7:3] of the interrupt vector that will be released during an interrupt acknowledge. A different base is selected for each interrupt controller. 5.7.2.3 ICW3 The third ...

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Functional Description 5.7.4.2 Special Fully-Nested Mode This mode will be used in the case of a system where cascading is used, and the priority has to be conserved within each slave. In this case, the special fully-nested mode will be ...

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Cascade Mode The PIC in the ICH4 has one master 8259 and one slave 8259 cascaded onto the master through IRQ2. This configuration can handle separate priority levels. The master controls the slaves through a three ...

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Functional Description 5.7.5 Masking Interrupts 5.7.5.1 Masking on an Individual Interrupt Request Each interrupt request can be masked individually by the Interrupt Mask Register (IMR). This register is programmed through OCW1. Each bit in the IMR masks one interrupt channel. ...

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Advanced Interrupt Controller (APIC) (D31:F0) In addition to the standard ISA-compatible Programmable Interrupt Controller (PIC) described in Section 5.7, the ICH4 incorporates the Advanced Programmable Interrupt Controller (APIC). While the standard interrupt controller is intended for use in a ...

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Functional Description Table 5-17. APIC Interrupt Mapping (Sheet Via IRQ # SERIRQ Yes 15 Yes 16 PIRQ[A]# 17 PIRQ[B]# 18 PIRQ[C]# 19 PIRQ[D]# 20 N/A 21 N/A 22 N/A 23 N/A NOTES: 1. IRQ ...

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When ICH4 detects a bus idle condition on the APIC Bus, and it has an interrupt to send over the APIC bus, it drives a start cycle to begin arbitration by driving bit APICCLK ...

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Functional Description EOI Message for Level Triggered Interrupts EOI messages are used by local APICs to send an EOI cycle occurring for a level-triggered interrupt to an I/O APIC. This message is needed so that the I/O APIC can differentiate ...

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Short Message Short messages are used for the delivery of Fixed, NMI, SMI, Reset, ExtINT, and Lowest Priority with Focus processor interrupts. The Delivery Mode bits (M2–M0) specify the message. All short messages take 21 cycles including the idle cycle. ...

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Functional Description Table 5-22. APIC Bus Status Cycle Definition Delivery Mode Fixed, EOI NMI, SMM, Reset, ExtINT Lowest Priority Remote Read 118 A Comments 11 Checksum OK 10 Error 01 Error 00 Checksum Error 11 Checksum OK 10 Error 01 ...

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Lowest Priority without Focus Processor (FP) Message This message format is used to deliver an interrupt in the lowest priority mode in which it does not have a Focus Process. Cycles 1 through 21 for this message is same as ...

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Functional Description Remote Read Message Remote read message is used when a local APIC wishes to read the register in another local APIC. The I/O APIC in the ICH4 neither generates or responds to this cycle. The message format is ...

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PCI Message-Based Interrupts 5.8.4.1 Theory of Operation The following scheme is only supported when the internal I/O(x) APIC is used (rather than just the 8259). The ICH4 supports the new method for PCI devices to deliver interrupts as write ...

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Functional Description 5.8.4.2 Registers and Bits Associated with PCI Interrupt Delivery Capabilities Indication The capability to support PCI interrupt delivery is indicated via ACPI configuration techniques. This involves the BIOS creating a data structure that gets reported to the ACPI ...

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Registers Associated with Processor System Bus Interrupt Delivery Capabilities Indication The capability to support Processor System Bus interrupt delivery is indicated via ACPI configuration techniques. This involves the BIOS creating a data structure that gets reported to the ACPI ...

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Functional Description Table 5-26. Interrupt Message Data Format Bit 31:16 Will always be 0000h. Trigger Mode Level Edge. Same as the corresponding bit in the I/O Redirection Table for 15 that interrupt. Delivery Status ...

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Start Frame The serial IRQ protocol has two modes of operation which affect the start frame. These two modes are: Continuous, where the ICH4 is solely responsible for generating the start frame; and Quiet, where a serial IRQ peripheral ...

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Functional Description 5.9.4 Specific Interrupts Not Supported via SERIRQ There are three interrupts seen through the serial stream which are not supported by the ICH4. These interrupts are generated internally and are not sharable with other devices within the system. ...

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Real Time Clock (D31:F0) The Real Time Clock (RTC) module provides a battery backed-up date and time keeping device with two banks of static RAM with 128 bytes each, although the first bank has 114 bytes for general purpose ...

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Functional Description 5.10.2 Interrupts The real-time clock interrupt is internally routed within the ICH4 both to the I/O APIC and the 8259 mapped to interrupt vector 8. This interrupt does not leave the ICH4, nor is it shared ...

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Table 5-29. Configuration Bits Reset By RTCRST# Assertion Bit Name FREQ_STRAP[3:0] AIE AF PWR_FLR AFTERG3_EN RTC_PWR_STS PRBTNOR_STS PME_EN RI_EN NEW_CENTURY_STS INTRD_DET TOP_SWAP RTC_EN Using a GPI to Clear CMOS A jumper on a GPI can also be used to clear ...

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Functional Description 5.11 Processor Interface (D31:F0) The ICH4 interfaces to the processor with a variety of signals • Standard Outputs to processor: A20M#, SMI#, NMI, INIT#, INTR, STPCLK#, IGNNE#, CPUSLP# • Standard Input from processor: FERR# Most ICH4 outputs to ...

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Table 5-30. INIT# Going Active Cause of INIT# Going Active Shutdown special cycle from processor. PORT92 write, where INIT_NOW (bit 0) transitions from PORTCF9 write, where RST_CPU (bit 2) was a 0 and SYS_RST(bit 1) ...

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Functional Description 5.11.1.4 NMI Non-Maskable Interrupts (NMIs) can be generated by several sources, as described in Table 5-31. NMI Sources Cause of NMI SERR# goes active (either internally, externally via SERR# signal, or via message from the MCH) IOCHK# goes ...

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Power Management Attempting clock control with more than one processor is not feasible, because the Host controller does not provide any indication as to which processor is executing a particular Stop-Grant cycle. Without this information, there is no way ...

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Functional Description 5.11.3 Speed Strapping for Processor The ICH4 directly sets the speed straps for the processor, saving the external logic that has been needed with prior PCIsets. Refer to processor specification for speed strapping definition. The ICH4 performs the ...

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Power Management (D31:F0) The power management features include: • ACPI Power and Thermal Management Support — ACPI 24-Bit Timer — Software initiated throttling of processor performance for Thermal and Power Reduction — Hardware Override to throttle processor performance if ...

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Functional Description Table 5-36 shows the transitions rules among the various states. Note that transitions among the various states may appear to temporarily transition through intermediate states. For example, in going from S0 to S1, it may appear to pass ...

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System Power Planes The system has several independent power planes, as described in particular power plane is shut off, it should level. s Table 5-37. System Power Plane Controlled Plane SLP_S3# Processor SLP_S3# MAIN ...

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Functional Description Table 5-38 shows which events can cause an SMI# and SCI. Note that some events can be programmed to cause either an SMI# or SCI. The usage of the event for SCI (instead of SMI#) is typically associated ...

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Table 5-38. Causes of SMI# and SCI (Sheet Cause Device monitors match address in its range SMBus Host controller SMBus Slave SMI message SMBus SMBALERT# signal active SMBus Host Notify message received Access microcontroller 62h/66h SLP_EN bit ...

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Functional Description The ICH4 supports the Pending Break Event (PBE) indication from the processor using the FERR# signal. The following rules apply: 1. When STPCLK# is detected active by the processor, the FERR# signal from the processor will be redefined ...

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Transition Rules among S0/Cx and Throttling States The following priority rules and assumptions apply among the various S0/Cx and throttling states: • Entry to any S0/Cx state is mutually exclusive with entry to any S1–S5 state. This is because ...

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Functional Description 5.12.6.2 Initiating Sleep State Sleep states (S1–S5) are initiated by: • Masking interrupts, turning off all bus master enable bits, setting the desired type in the SLP_TYP field, and then setting the SLP_EN bit. The hardware will then ...

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Table 5-41. Causes of Wake Events Cause RTC Alarm Power Button GPI[0:n] USB LAN RI# AC ’97 Primary PME# Secondary PME# SMBALERT# SMBus Slave Message SMBus Host Notify message received PME_B0 (internal USB EHCI controller) NOTES: 1. This will be ...

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Functional Description 5.12.6.4 Sx-G3-Sx, Handling Power Failures In desktop systems, power failures can occur if the AC power is cut (a real power failure the system is unplugged. In either case, PWROK and RSMRST# are assumed to go ...

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Thermal Management The ICH4 has mechanisms to assist with managing thermal problems in the system. 5.12.7.1 THRM# Signal The THRM# signal is used as a status input for a thermal sensor. Based on the THRM# signal going active, the ...

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Functional Description 5.12.7.4 Processor-Initiated Passive Cooling (Via Programmed Duty Cycle on STPCLK#) Using the THTL_EN and THTL_DTY bits, the ICH4 can force a programmed duty cycle on the STPCLK# signal. This reduces the effective instruction rate of the processor and ...

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Sleep Button The ACPI specification defines an optional Sleep button. It differs from the power button in that it only is a request to go from S0 to S1–S4 (not S5). Also state, the Power Button can ...

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Functional Description 5.12.8.5 THRMTRIP# Signal If THRMTRIP# goes active, the processor is indicating an overheat condition, and the ICH4 immediately transitions state. However, since the processor has overheated, it does not respond to the ICH4’s STPCLK# pin ...

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For other operating systems (e.g., MS-DOS) the BIOS should restore the timer back to 54.6 ms before passing control to the OS. If the BIOS is entering ALT access mode before entering the suspend state it is not necessary to ...

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Functional Description Table 5-46. Write Only Registers with Read Paths in ALT Access Mode (Sheet Restore Data I Access Addr Rds 1 PIC ICW2 of Master controller 2 PIC ICW3 of Master controller 3 PIC ...

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Read Only Registers with Write Paths in ALT Access Mode The registers described in restores these values after returning from a powered down state. These registers must be handled special by software. When in normal mode, writing to the ...

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Functional Description 5.12.10.4 Controlling Leakage and Power Consumption during Low-Power States To control leakage in the system, various signals tri-state or go low during some low-power states. General principles: • All signals going to powered down planes (either internally or ...

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Legacy Power Management Theory of Operation Instead of relying on ACPI software, legacy power management uses BIOS and various hardware mechanisms. ICH4 has a greatly simplified method for legacy power management compared with previous generations (e.g., the PIIX4). The ...

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Functional Description 5.13 System Management (D31:F0) The ICH4 provides various functions to make a system easier to manage and to lower the Total Cost of Ownership (TCO) of the system. Features and functions can be augmented via external A/D converters ...

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If the INTRUDER# signal goes inactive some point after the INTRD_DET bit is written then the INTRD_DET signal will when INTRUDER# input signal goes inactive. Note that this is slightly different than a ...

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Functional Description The following rules/steps apply if the system state and the policy is for the ICH4 to reboot the system after a hardware lockup: 1. Upon detecting the lockup the SECOND_TO_STS bit will be set. ...

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After step 4 (power button override), if the user presses the power button again, the system should wake state and the processor should start executing the BIOS step 5 (power button press) is successful ...

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Functional Description 2. WARNING important that the BIOS clears the SECOND_TO_STS bit, as the alerts will interfere with the LAN device driver from working properly. The alerts reset part of the D110 and would prevent an operating system’s ...

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General Purpose I/O 5.14.1 GPIO Mapping Table 5-51. GPIO Implementation (Sheet GPIO Type Input GPI[0] Only Input GPI[1] Only Input GPI[2:5] Only Input GPI[6] Only Input GPI[7] Only Input GPI[8] Only GPIO[9:10] N/A Input GPI[11] Only ...

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Functional Description Table 5-51. GPIO Implementation (Sheet GPIO Type Output GPO[16] Only Output GPO[17] Only Output GPO[18] Only Output GPO[19] Only Output GPO[20] Only Output GPO[21] Only Output GPO[22] Only Output GPIO[23 Only GPIO[24] I/O GPIO[25] I/O ...

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Power Wells Some GPIOs exist in the resume power plane. Care must be taken to make sure GPIO signals are not driven high into powered-down planes. Some ICH4 GPIOs may be connected to pins on devices that exist in ...

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Functional Description 5.15.1 PIO Transfers The ICH4 IDE controller includes both compatible and fast timing modes. The fast timing modes can be enabled only for the IDE data ports. All other transactions to the IDE registers are run in single ...

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Table 5-52. IDE Legacy I/O Ports: Command Block Registers (CS1x# Chip Select) I/O Offset 00h Data 01h Error 02h Sector Count 03h Sector Number 04h Cylinder Low 05h Cylinder High 06h Drive 07h Status NOTE: For accesses to the Alt ...

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Functional Description Table 5-53. IDE Transaction Timings (PCI Clocks) IDE Transaction Type Non-Data Port Compatible Data Port Compatible Fast Timing Mode 5.15.1.4 IORDY Masking The IORDY signal can be ignored and assumed asserted at the first IORDY Sample Point (ISP) ...

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Physical Region Descriptor Format The physical memory region to be transferred is described by a Physical Region Descriptor (PRD). The PRDs are stored sequentially in a Descriptor Table in memory. The data transfer proceeds until all regions described by ...

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Functional Description 5.15.2.3 Bus Master IDE Timings The timing modes used for Bus Master IDE transfers are identical to those for PIO transfers. The DMA Timing Enable Only bits in the IDE Timing register can be used to program fast ...

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Current Base and Current Count registers. These registers hold the current value of the address and byte count loaded from the PRD table. The value in these registers is only valid when there is an active ...

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Functional Description Table 5-54. Interrupt/Active Bit Interaction Definition Interrupt Active 5.15.2.6 Error Conditions IDE devices are sector-based mass storage devices. The drivers handle errors on a sector basis; either a sector is ...

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Signal Descriptions The Ultra ATA/33 protocol requires no extra signal pins on the IDE connector. It does redefine a number of the standard IDE control signals when in Ultra ATA/33 mode. These redefinitions are shown in Table 5-55. Read ...

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Functional Description The data transfer phase continues the burst transfers with the data transmitter (ICH4 - writes, IDE device - reads) providing data and toggling STROBE. Data is transferred (latched by receiver) on each rising and falling edge of STROBE. ...

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Ultra ATA/33/66/100 Timing The timings for Ultra ATA/33/66/100 modes are programmed via the Synchronous DMA Timing Register and the IDE Configuration Register. Different timings can be programmed for each drive in the system. The Base Clock frequency for each ...

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Functional Description 5.16 USB UHCI Controllers (D29:F0, F1 and F2) The ICH4 contains three USB UHCI Host controllers. Each Host controller includes a root hub with two separate USB ports each, for a total of 6 USB ports. The ICH4 ...

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Transfer Descriptor (TD) Transfer Descriptors (TDs) express the characteristics of the transaction requested on USB by a client. TDs are always aligned on 16-byte boundaries, and the elements of the TD are shown in Figure 5-15. The 4 different ...

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Functional Description Table 5-58. TD Control and Status (Sheet Bit 31:30 Reserved. Short Packet Detect (SPD). When a packet has this bit set to 1 and the packet is an input packet queue; and ...

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Table 5-58. TD Control and Status (Sheet Bit Stalled Set the ICH4 during status updates to indicate that a serious error has occurred at the device/endpoint addressed by this TD. This ...

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Functional Description Table 5-59. TD Token Bit Maximum Length (MAXLEN). The Maximum Length field specifies the maximum number of data bytes allowed for the transfer. The Maximum Length value does not include protocol bytes, such as Packet ID (PID) and ...

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Queue Head (QH) Queue heads are special structures used to support the requirements of Control, Bulk, and Interrupt transfers. Since these TDs are not automatically retired after each use, their maintenance requirements can be reduced by putting them into ...

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Functional Description 5.16.2 Data Transfers to/from Main Memory The following sections describe the details on how HCD and the ICH4 communicate via the Schedule data structures. The discussion is organized in a top-down manner, beginning with the basics of walking ...

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Processing Transfer Descriptors The ICH4 executes a TD using the following generalized algorithm. These basic steps are common across all modes of TDs. Subsequent sections present processing steps unique to each TD mode. 1. ICH4 fetches ...

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Functional Description 5.16.2.3 Command Register, Status Register, and TD Status Bit Interaction Table 5-64. Command Register, Status Register, and TD Status Bit Interaction Condition CRC/Time Out Error Illegal PID, PID Error, Max Length (illegal) PCI Master/Target Abort Suspend Mode Resume ...

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Transfer Queuing Transfer Queues are used to implement a guaranteed data delivery stream to a USB Endpoint. Transfer Queues are composed of two parts: a Queue Header (QH) and a linked list. The linked list of TDs and QHs ...

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Functional Description Transfer Queues are based on the following characteristics: • A QH’s vertical link pointer (Queue Element Link Pointer) references the “Top” queue member. A QH’s horizontal link pointer (Queue Head Link Pointer) references the “next” work element in ...

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Legends: QH.LP = Queue Head Link Pointer (or Horizontal Link Pointer) QE.LP = Queue Element Link Pointer (or Vertical Link Pointer) TD. Link Pointer QH bit bit in QH Table 5-66. ...

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Functional Description 5.16.3 Data Encoding and Bit Stuffing The USB employs NRZI data encoding (Non-Return to Zero Inverted) when transmitting packets. In NRZI encoding; a one is represented by no change in level, and a zero is represented by a ...

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Table 5-67. PID Format Bit Packet Identifier Field A packet identifier (PID) immediately follows the SYNC field of every USB packet. A PID consists of a four bit packet type field followed by a four-bit check ...

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Functional Description 5.16.4.4 Address Fields Function endpoints are addressed using two fields: the function address field and the endpoint field. Table 5-69. Address Field Bit Address Field The function address (ADDR) field specifies the function, via ...

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Cyclic Redundancy Check (CRC) CRC is used to protect the all non-PID fields in token and data packets. In this context, these fields are considered to be protected fields. The PID is not included in the CRC check of ...

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Functional Description Table 5-72. SOF Packet Packet PID Frame Number CRC5 5.16.5.3 Data Packets A data packet consists of a PID, a data field, and a CRC as shown in types of data packets, identified by differing PIDs: DATA0 and ...

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Handshake Responses IN Transaction A function may respond transaction with a STALL or NAK. If the token received was corrupted, the function will issue no response. If the function can transmit data, it will issue the ...

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Functional Description When the C_ERR field decrements to zero, the following occurs: • The Active bit in the TD is cleared • The Stalled bit in the TD is set • The CRC/Time-out bit in the TD is set. • ...

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Data Buffer Error This event indicates that an overrun of incoming data or a under-run of outgoing data has occurred for this transaction. This would generally be caused by the ICH4 not being able to access required data buffers in ...

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Functional Description 5.16.7 USB Power Management The Host controller can be put into a suspended state and its power can be removed. This requires that certain bits of information are retained in the resume power plane of the ICH4 so ...

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Figure 5-18. USB Legacy Keyboard Enable and Status Paths KBC Accesses PCI Config Read, Write USB_IRQ Clear USB_IRQ ® Intel 82801DB ICH4 Datasheet 60 READ S D Clear SMI_60_R Comb. R Decoder EN_SMI_ON_60R Same for 60W, 64R, 64W EN_PIRQD# AND ...

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Functional Description Table 5-75. USB Legacy Keyboard State Transitions Current State Action IDLE 64h / Write IDLE 64h / Write IDLE 64h / Read IDLE 60h / Write IDLE 60h / Read GateState1 60h / Write GateState1 64h / Write ...

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USB EHCI Controller (D29:F7) The ICH4 contains an Enhanced Host Controller Interface (EHCI) compliant host controller which supports up to six, high-speed USB 2.0 Specification compliant root ports. High-speed USB 2.0 allows data transfers up to 480 Mbps using ...

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Functional Description 5.17.1.3 Driver Initialization See Chapter 4 of the Enhanced Host Controller Interface Specification for Universal Serial Bus. 5.17.1.4 EHC Resets In addition to the standard ICH4 hardware resets, portions of the EHC are reset by the HCRESET bit ...

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Periodic List Execution The Periodic DMA engine contains buffering for two control structures (two transactions). By implementing two entries, the EHC is able to pipeline the memory accesses for the next transaction while executing the current transaction on the ...

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Functional Description 5.17.3.1.2 Write Policies for Periodic DMA The Periodic DMA engine performs writes for the following reasons. Memory Structure iTD Status Write siTD Status Write Interrupt Queue Head Overlay Interrupt Queue Head Status Write Interrupt qTD Status Write In ...

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Note: The ADE does not fetch data when encountered in the Ping state. An Ack handshake in response to the Ping results in the ADE writing the QH to the Out state, which results in the fetching ...

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Functional Description 5.17.6 USB EHCI Interrupts and Error Conditions Section 4 of the EHCI specification goes into detail on the EHC interrupts and the error conditions that cause them. All error conditions that the EHC detects can be reported through ...

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