FW82801FB Intel Corporation, FW82801FB Datasheet

no-image

FW82801FB

Manufacturer Part Number
FW82801FB
Description
Intel 82801FB I/O Controller Hub (ICH6)
Manufacturer
Intel Corporation
Datasheet

Specifications of FW82801FB

Dc
0625

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
FW82801FB
Manufacturer:
INTEL
Quantity:
103
Part Number:
FW82801FB
Manufacturer:
INTEL
Quantity:
253
Part Number:
FW82801FB SL7AG
Manufacturer:
SHARP
Quantity:
200
Part Number:
FW82801FB SL7AG
Manufacturer:
INTEL
Quantity:
57
Part Number:
FW82801FB-QF88ES
Manufacturer:
INTEL
Quantity:
51
Part Number:
FW82801FBM
Manufacturer:
ATMEL
Quantity:
4
Part Number:
FW82801FBM SL7W6
Manufacturer:
INTEL
Quantity:
56
®
Intel
I/O Controller Hub 6 (ICH6)
Family
Datasheet
®
For the Intel
82801FB ICH6, 82801FR ICH6R and 82801FBM ICH6-M
I/O Controller Hubs
January 2005
Document Number: 301473-002

Related parts for FW82801FB

FW82801FB Summary of contents

Page 1

Intel I/O Controller Hub 6 (ICH6) Family Datasheet ® For the Intel 82801FB ICH6, 82801FR ICH6R and 82801FBM ICH6-M I/O Controller Hubs January 2005 Document Number: 301473-002 ...

Page 2

... Corporation. Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM. Intel, Intel SpeedStep and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. ...

Page 3

Contents 1 Introduction ............................................................................................................................. 43 1.2 Overview............................................................................................................................. 46 2 Signal Description ................................................................................................................. 53 2.1 Direct Media Interface (DMI) to Host Controller.................................................................. 56 2.2 PCI Express* ...................................................................................................................... 56 2.3 Link to LAN Connect ...........................................................................................................57 2.4 EEPROM Interface ............................................................................................................. 57 2.5 Firmware ...

Page 4

Contents 5.1.2.2 I/O Reads and Writes............................................................................. 98 5.1.2.3 Configuration Reads and Writes ............................................................ 98 5.1.2.4 Locked Cycles........................................................................................ 98 5.1.2.5 Target / Master Aborts ........................................................................... 98 5.1.2.6 Secondary Master Latency Timer .......................................................... 98 5.1.2.7 Dual Address Cycle (DAC) .................................................................... 98 5.1.2.8 ...

Page 5

LPC Interface .......................................................................................................116 5.5.1.1 LPC Cycle Types .................................................................................117 5.5.1.2 Start Field Definition.............................................................................117 5.5.1.3 Cycle Type / Direction (CYCTYPE + DIR) ...........................................118 5.5.1.4 SIZE .....................................................................................................118 5.5.1.5 SYNC ...................................................................................................119 5.5.1.6 SYNC Time-Out ...................................................................................119 5.5.1.7 SYNC Error Indication..........................................................................119 5.5.1.8 LFRAME# Usage .................................................................................119 ...

Page 6

Contents 5.9.4.4 Specific Rotation Mode (Specific Priority)............................................ 135 5.9.4.5 Poll Mode ............................................................................................. 135 5.9.4.6 Cascade Mode..................................................................................... 136 5.9.4.7 Edge and Level Triggered Mode.......................................................... 136 5.9.4.8 End of Interrupt (EOI) Operations ........................................................ 136 5.9.4.9 Normal End of Interrupt........................................................................ 136 5.9.4.10 Automatic ...

Page 7

SMI#/SCI Generation...........................................................................................153 5.14.4.1 PCI Express* SCI.................................................................................155 5.14.4.2 PCI Express* Hot-Plug.........................................................................155 5.14.5 Dynamic Processor Clock Control .......................................................................156 5.14.5.1 Transition Rules among S0/Cx and Throttling States ..........................157 5.14.5.2 Deferred C3/C4 (Mobile Only) .............................................................157 5.14.5.3 POPUP (Auto C3/C4 to C2) (Mobile Only) ...

Page 8

Contents 5.15.1.1 Detecting a System Lockup ................................................................. 174 5.15.1.2 Handling an Intruder ............................................................................ 174 5.15.1.3 Detecting Improper Firmware Hub Programming ................................ 175 5.15.2 Heartbeat and Event Reporting via SMBus ......................................................... 175 5.16 IDE Controller (D31:F1) .................................................................................................... 179 5.16.1 PIO Transfers ...

Page 9

Frame Number Field ............................................................................195 5.19.4.6 Data Field.............................................................................................195 5.19.4.7 Cyclic Redundancy Check (CRC) ........................................................195 5.19.5 Packet Formats....................................................................................................195 5.19.6 USB Interrupts .....................................................................................................195 5.19.6.1 Transaction-Based Interrupts...............................................................196 5.19.6.2 Non-Transaction Based Interrupts .......................................................198 5.19.7 USB Power Management ....................................................................................198 5.19.8 USB Legacy Keyboard Operation........................................................................199 5.20 ...

Page 10

Contents 5.22.2.1 Register Access ................................................................................... 230 5.22.3 AC-Link Low Power Mode ................................................................................... 231 5.22.3.1 External Wake Event ........................................................................... 232 5.22.4 AC ’97 Cold Reset ............................................................................................... 233 5.22.5 AC ’97 Warm Reset ............................................................................................. 233 5.22.6 Hardware Assist to Determine ACZ_SDIN Used ...

Page 11

CSIR6—Chipset Initialization Register 6 .............................................................258 7.1.29 BCR—Backbone Configuration Register .............................................................259 7.1.30 RPC—Root Port Configuration Register..............................................................259 7.1.31 CSIR7—Chipset Initialization Register 7 .............................................................260 7.1.32 TRSR—Trap Status Register...............................................................................260 7.1.33 TRCR—Trapped Cycle Register..........................................................................260 7.1.34 TWDR—Trapped Write Data Register.................................................................261 7.1.35 IOTRn—I/O Trap Register(0:3)............................................................................261 7.1.36 ...

Page 12

Contents 8.1.6 SCC—Sub Class Code Register (LAN Controller—B1:D8:F0) ................................................................................ 285 8.1.7 BCC—Base-Class Code Register (LAN Controller—B1:D8:F0) ................................................................................ 285 8.1.8 CLS—Cache Line Size Register (LAN Controller—B1:D8:F0) ................................................................................ 286 8.1.9 PMLT—Primary Master Latency Timer Register (LAN Controller—B1:D8:F0) ................................................................................ 286 8.1.10 HEADTYP—Header Type ...

Page 13

REC_DMA_BC—Receive DMA Byte Count Register (LAN Controller—B1:D8:F0) ................................................................................300 8.2.8 EREC_INTR—Early Receive Interrupt Register (LAN Controller—B1:D8:F0) ................................................................................301 8.2.9 FLOW_CNTL—Flow Control Register (LAN Controller—B1:D8:F0) ................................................................................302 8.2.10 PMDR—Power Management Driver Register (LAN Controller—B1:D8:F0) ................................................................................303 8.2.11 GENCNTL—General Control Register (LAN Controller—B1:D8:F0) ................................................................................304 8.2.12 ...

Page 14

Contents 8.3.18 SP_MODE—Special Modes Register (ASF Controller—B1:D8:F0) ................................................................................ 319 8.3.19 INPOLL_TCONF—Inter-Poll Timer Configuration Register (ASF Controller—B1:D8:F0) ................................................................................ 319 8.3.20 PHIST_CLR—Poll History Clear Register (ASF Controller—B1:D8:F0) ................................................................................ 320 8.3.21 PMSK1—Polling Mask 1 Register (ASF Controller—B1:D8:F0) ................................................................................ 320 8.3.22 PMSK2—Polling Mask 2 ...

Page 15

BCTRL—Bridge Control Register (PCI-PCI—D30:F0) ........................................335 9.1.20 SPDH—Secondary PCI Device Hiding Register (PCI-PCI—D30:F0) ..............................................................................................336 9.1.21 PDPR—PCI Decode Policy Register (PCI-PCI—D30:F0) ..............................................................................................337 9.1.22 DTC—Delayed Transaction Control Register (PCI-PCI—D30:F0) ..............................................................................................338 9.1.23 BPS—Bridge Proprietary Status Register (PCI-PCI—D30:F0) ..............................................................................................339 9.1.24 BPC—Bridge Policy Configuration Register ...

Page 16

Contents 10.1.26 BIOS_CNTL—BIOS Control Register (LPC I/F—D31:F0)............................................................................................... 360 10.1.27 RCBA—Root Complex Base Address Register (LPC I/F—D31:F0)............................................................................................... 361 10.2 DMA I/O Registers (LPC I/F—D31:F0)............................................................................. 361 10.2.1 DMABASE_CA—DMA Base and Current Address Registers (LPC I/F—D31:F0)............................................................................... 363 10.2.2 DMABASE_CC—DMA Base and Current Count ...

Page 17

IND—Index Register (LPC I/F—D31:F0) .............................................................380 10.5.3 DAT—Data Register (LPC I/F—D31:F0) .............................................................381 10.5.4 EOIR—EOI Register (LPC I/F—D31:F0) .............................................................381 10.5.5 ID—Identification Register (LPC I/F—D31:F0) ....................................................382 10.5.6 VER—Version Register (LPC I/F—D31:F0) ........................................................382 10.5.7 REDIR_TBL—Redirection Table (LPC I/F—D31:F0) ..........................................383 10.6 Real Time Clock ...

Page 18

Contents 10.8.3.5 PROC_CNT—Processor Control Register .......................................... 408 10.8.3.6 LV2 — Level 2 Register ....................................................................... 410 10.8.3.7 LV3—Level 3 Register (Mobile Only)................................................... 410 10.8.3.8 LV4—Level 4 Register (Mobile Only)................................................... 410 10.8.3.9 PM2_CNT—Power Management 2 Control (Mobile Only) .................. 411 10.8.3.10 GPE0_STS—General ...

Page 19

PCMD_BAR—Primary Command Block Base Address Register (IDE—D31:F1).......................................................................................442 11.1.12 PCNL_BAR—Primary Control Block Base Address Register (IDE—D31:F1).......................................................................................443 11.1.13 SCMD_BAR—Secondary Command Block Base Address Register (IDE D31:F1) .........................................................................................443 11.1.14 SCNL_BAR—Secondary Control Block Base Address Register (IDE D31:F1) .........................................................................................443 11.1.15 BM_BASE — Bus ...

Page 20

Contents 12.1.10 PCMD_BAR—Primary Command Block Base Address Register (SATA–D31:F2)..................................................................................... 461 12.1.11 PCNL_BAR—Primary Control Block Base Address Register (SATA–D31:F2) ................................................................................................... 461 12.1.12 SCMD_BAR—Secondary Command Block Base Address Register (IDE D31:F1) ......................................................................................... 462 12.1.13 SCNL_BAR—Secondary Control Block Base Address Register (IDE D31:F1) ...

Page 21

ATS—APM Trapping Status Register (SATA–D31:F2) .......................................480 12.1.42 SP—Scratch Pad Register (SATA–D31:F2) ........................................................480 12.1.43 BFCS—BIST FIS Control/Status Register (SATA–D31:F2) ................................480 12.1.44 BFTD1—BIST FIS Transmit Data1 Register (SATA–D31:F2).............................482 12.1.45 BFTD2—BIST FIS Transmit Data2 Register (SATA–D31:F2).............................482 12.2 Bus Master IDE I/O Registers ...

Page 22

Contents 13.1.9 MLT—Master Latency Timer Register (USB—D29:F0/F1/F2/F3) .................................................................................... 510 13.1.10 HEADTYP—Header Type Register (USB—D29:F0/F1/F2/F3) .................................................................................... 511 13.1.11 BASE—Base Address Register (USB—D29:F0/F1/F2/F3) .................................................................................... 511 13.1.12 SVID — Subsystem Vendor Identification Register (USB—D29:F0/F1/F2/F3) .................................................................................... 512 13.1.13 SID — Subsystem Identification Register (USB—D29:F0/F1/F2/F3) ...

Page 23

MEM_BASE—Memory Base Address Register (USB EHCI—D29:F7) ..........................................................................................532 14.1.11 SVID—USB EHCI Subsystem Vendor ID Register (USB EHCI—D29:F7) ..........................................................................................532 14.1.12 SID—USB EHCI Subsystem ID Register (USB EHCI—D29:F7) ..........................................................................................533 14.1.13 CAP_PTR—Capabilities Pointer Register (USB EHCI—D29:F7) ..........................................................................................533 14.1.14 INT_LN—Interrupt Line Register (USB EHCI—D29:F7) ...

Page 24

Contents 14.2.2.2 USB2.0_STS—USB 2.0 Status Register ............................................. 550 14.2.2.3 USB2.0_INTR—USB 2.0 Interrupt Enable Register ............................ 552 14.2.2.4 FRINDEX—Frame Index Register ....................................................... 553 14.2.2.5 CTRLDSSEGMENT—Control Data Structure Segment Register................................................................................................ 554 14.2.2.6 PERIODICLISTBASE—Periodic Frame List Base Address Register................................................................................................ 554 14.2.2.7 ASYNCLISTADDR—Current Asynchronous ...

Page 25

AUX_CTL—Auxiliary Control Register (SMBus—D31:F3) ..................................576 15.2.13 SMLINK_PIN_CTL—SMLink Pin Control Register (SMBus—D31:F3) ...............................................................................................576 15.2.14 SMBus_PIN_CTL—SMBus Pin Control Register (SMBus—D31:F3) ...............................................................................................577 15.2.15 SLV_STS—Slave Status Register (SMBus—D31:F3).........................................577 15.2.16 SLV_CMD—Slave Command Register (SMBus—D31:F3) .................................578 15.2.17 NOTIFY_DADDR—Notify Device Address Register (SMBus—D31:F3) ...............................................................................................578 15.2.18 NOTIFY_DLOW—Notify ...

Page 26

Contents 16.2.2 x_CIV—Current Index Value Register (Audio—D30:F2) ..................................... 597 16.2.3 x_LVI—Last Valid Index Register (Audio—D30:F2) ............................................ 597 16.2.4 x_SR—Status Register (Audio—D30:F2)............................................................ 598 16.2.5 x_PICB—Position In Current Buffer Register (Audio—D30:F2).................................................................................................. 599 16.2.6 x_PIV—Prefetched Index Value Register (Audio—D30:F2)................................ 599 16.2.7 x_CR—Control Register ...

Page 27

CAS—Codec Access Semaphore Register (Modem—D30:F3) ...............................................................................................625 ® 18 Intel High Definition Audio Controller Registers (D27:F0) ® 18.1 Intel High Definition Audio PCI Configuration Space ® (Intel High Definition Audio— D27:F0)............................................................................627 18.1.1 VID—Vendor Identification Register ® (Intel High Definition Audio ...

Page 28

Contents 18.1.23 PCS—Power Management Control and Status Register ® (Intel High Definition Audio Controller—D27:F0) ............................................... 638 18.1.24 MID—MSI Capability ID Register ® (Intel High Definition Audio Controller—D27:F0) ............................................... 638 18.1.25 MMC—MSI Message Control Register ® (Intel High Definition Audio Controller—D27:F0) ...

Page 29

L1ADDU—Link 1 Upper Address Register ® (Intel High Definition Audio Controller—D27:F0) ...............................................649 ® 18.2 Intel High Definition Audio Memory Mapped Configuration Registers ® (Intel High Definition Audio— D27:F0)............................................................................649 18.2.1 GCAP—Global Capabilities Register ® (Intel High Definition Audio Controller—D27:F0) ...............................................653 ...

Page 30

Contents 18.2.25 RIRBCTL—RIRB Control Register ® (Intel High Definition Audio Controller—D27:F0) ............................................... 664 18.2.26 RIRBSTS—RIRB Status Register ® (Intel High Definition Audio Controller—D27:F0) ............................................... 664 18.2.27 RIRBSIZE—RIRB Size Register ® (Intel High Definition Audio Controller—D27:F0) ............................................... 665 18.2.28 IC—Immediate Command ...

Page 31

PI—Programming Interface Register (PCI Express—D28:F0/F1/F2/F3)........................................................................681 19.1.7 SCC—Sub Class Code Register (PCI Express—D28:F0/F1/F2/F3)........................................................................681 19.1.8 BCC—Base Class Code Register (PCI Express—D28:F0/F1/F2/F3)........................................................................681 19.1.9 CLS—Cache Line Size Register (PCI Express—D28:F0/F1/F2/F3)........................................................................682 19.1.10 PLT—Primary Latency Timer Register (PCI Express—D28:F0/F1/F2/F3)........................................................................682 19.1.11 HEADTYP—Header Type Register (PCI Express—D28:F0/F1/F2/F3)........................................................................682 ...

Page 32

Contents 19.1.32 SLSTS—Slot Status Register (PCI Express—D28:F0/F1/F2/F3) ....................................................................... 697 19.1.33 RCTL—Root Control Register (PCI Express—D28:F0/F1/F2/F3) ....................................................................... 698 19.1.34 RSTS—Root Status Register (PCI Express—D28:F0/F1/F2/F3) ....................................................................... 698 19.1.35 MID—Message Signaled Interrupt Identifiers Register (PCI Express—D28:F0/F1/F2/F3) ....................................................................... 699 19.1.36 MC—Message Signaled Interrupt Message ...

Page 33

AECC — Advanced Error Capabilities and Control Register (PCI Express—D28:F0/F1/F2/F3)........................................................................711 19.1.59 RES — Root Error Status Register (PCI Express—D28:F0/F1/F2/F3)........................................................................711 19.1.60 RCTCL — Root Complex Topology Capability List Register (PCI Express—D28:F0/F1/F2/F3)........................................................................711 19.1.61 ESD — Element Self Description Register (PCI Express—D28:F0/F1/F2/F3)........................................................................712 ...

Page 34

Contents Figures 1 Desktop Configuration ................................................................................................................ 42 2 Mobile Configuration................................................................................................................... 42 ® 2-1 Intel ICH6 Interface Signals Block Diagram (Desktop)............................................................. 54 ® 2-2 Intel ICH6-M Interface Signals Block Diagram (Mobile Only)................................................... 55 2-3 Example External RTC Circuit .................................................................................................... 76 4-1 ...

Page 35

Timings, S3 22-26S0 Timings, S3 22-27C0 Timings (Mobile Only) ....................................................................................773 22-28C0 Timings (Mobile Only) ....................................................................................774 22-29C0 Timings (Mobile Only) ...

Page 36

Contents 5-5 Start Field Bit Definitions .......................................................................................................... 117 5-6 Cycle Type Bit Definitions......................................................................................................... 118 5-7 Transfer Size Bit Definition ....................................................................................................... 118 5-8 SYNC Bit Definition .................................................................................................................. 119 5-9 DMA Transfer Size ................................................................................................................... 123 5-10 Address Shifting in 16-Bit I/O DMA ...

Page 37

Host Notify Format....................................................................................................................225 5-56 Features Supported by Intel 5-57 Output Tag Slot 0......................................................................................................................231 6-1 PCI Devices and Functions ......................................................................................................238 6-2 Fixed I/O Ranges Decoded by Intel 6-3 Variable I/O Decode Ranges ....................................................................................................242 6-4 Memory Decode Ranges from Processor Perspective.............................................................243 ...

Page 38

Contents ® 17-2 Intel ICH6 Modem Mixer Register Configuration .................................................................... 616 17-3 Modem Registers ..................................................................................................................... 617 ® 18-1 Intel High Definition Audio PCI Register Address Map ® (Intel High Definition Audio D27:F0) ....................................................................................... 627 ® 18-2 Intel High Definition Audio ...

Page 39

Revision History Revision -001 Initial release. • Added ICH6-M content • Removed support for Wireless SKUs. -002 • Added all specification clarifications, changes and document changes from Specification Updates. ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Description Contents ...

Page 40

Contents ® Intel ICH6 Family Features New: Direct Media Interface — 10 Gb/s each direction, full duplex — Transparent to software New: PCI Express* — 4 PCI Express root ports — Fully PCI Express 1.0a compliant — Can be statically ...

Page 41

SMBus — New: Flexible SMBus/SMLink architecture to optimize for ASF — Provides independent manageability bus through SMLink interface — Supports SMBus 2.0 Specification — Host interface allows processor to communicate via SMBus — Slave interface allows an internal or external ...

Page 42

Contents Figure 1. Desktop Configuration ® Intel PCI Express Gigabit Ethernet Figure 2. Mobile Configuration 42 USB 2.0 (Supports 8 USB ports) IDE SATA (4 ports) ® AC ’97/Intel High ® Intel Definition Audio Codec(s) PCI Express* x1 LAN Connect ...

Page 43

Introduction This document is intended for Original Equipment Manufacturers and BIOS vendors creating ® Intel I/O Controller Hub 6 (ICH6) Family (ICH6, ICH6R, and ICH6-M) based products. This document is the datasheet for the following: ® • Intel 82801FB ...

Page 44

Introduction Table 1-1. Industry Specifications (Sheet Alert Standard Format Specification, Version 1.03 AT Attachment - 6 with Packet Interface (ATA/ATAPI - 6) IA-PC HPET (High Precision Event Timers) Specification, Revision 0.98a Chapter 1. Introduction Chapter 1 introduces ...

Page 45

Chapter 10. LPC Bridge Registers Chapter 10 provides a detailed description of all registers that reside in the LPC bridge. This bridge resides at Device 31, Function 0 (D31:F0). This function contains registers for many different units within the ICH6 ...

Page 46

Introduction Chapter 23. Package Information Chapter 23 provides drawings of the physical dimensions and characteristics of the 609-mBGA package. Chapter 24. Testability Chapter 24 provides detail about the implementation of test modes provided in the ICH6. 1.2 Overview The ICH6 ...

Page 47

Table 1-2. PCI Devices and Functions Bus:Device:Function Bus 0:Device 30:Function 0 Bus 0:Device 30:Function 2 Bus 0:Device 30:Function 3 Bus 0:Device 31:Function 0 Bus 0:Device 31:Function 1 Bus 0:Device 31:Function 2 Bus 0:Device 31:Function 3 Bus 0:Device 29:Function 0 Bus ...

Page 48

Introduction Serial ATA (SATA) Controller The ICH6 has an integrated SATA host controller that supports independent DMA operation on four ports (desktop only) or two ports (mobile only) and supports data transfer rates 1.5 Gb/s (150 MB/s). ...

Page 49

Compatibility Modules (DMA Controller, Timer/Counters, Interrupt Controller) The DMA controller incorporates the logic of two 82C37 DMA controllers, with seven independently programmable channels. Channels 0–3 are hardwired to 8-bit, count-by-byte transfers, and channels 5–7 are hardwired to 16-bit, count-by-word transfers. ...

Page 50

Introduction The LAN controller can operate in either full duplex or half duplex mode. In full duplex mode the LAN controller adheres with the IEEE 802.3x Flow Control specification. Half duplex performance is enhanced by a proprietary collision reduction mechanism. ...

Page 51

TCO Timer. The ICH6’s integrated programmable TCO timer is used to detect system locks. The first expiration of the timer generates an SMI# that the system can use to recover from a software lock. The second expiration of the ...

Page 52

Introduction The Intel High Definition Audio controller utilizes multi-purpose DMA engines, as opposed to dedicated DMA engines in AC ’97, to effectively manage the link bandwidth and support simultaneous independent streams on the link. The capability enables new exciting usage ...

Page 53

Signal Description This chapter provides a detailed description of each signal. The signals are arranged in functional groups according to their associated interface. The “#” symbol at the end of the signal name indicates that the active, or asserted ...

Page 54

Signal Description ® Figure 2-1. Intel ICH6 Interface Signals Block Diagram (Desktop) REQ[4]# / GPI[40] REQ[5]# / GPI[1] REQ[6]# / GPI[0] GNT[4]# / GPO[48] GNT[5]# / GPO[17] GNT[6]# / GPO[16] CPUPWRGD / GPO[49] PIRQ[H:E]# / GPIO[5:2] OC[4]# / GPI[9] OC[5]# ...

Page 55

Figure 2-2. Intel ICH6-M Interface Signals Block Diagram (Mobile Only) REQ[4]# / GPI[40] REQ[5]# / GPI[1] REQ[6]# / GPI[0] GNT[4]# / GPO[48] GNT[5]# / GPO[17] GNT[6]# / GPO[16] CPUPWRGD / GPO[49] PIRQ[H:E]# / GPI[5:2] OC[4]# / GPI[9] OC[5]# / ...

Page 56

Signal Description 2.1 Direct Media Interface (DMI) to Host Controller Table 2-1. Direct Media Interface Signals Name Type DMI[0]TXP, DMI[0]TXN DMI[0]RXP, DMI[0]RXN DMI[1]TXP, DMI[1]TXN DMI[1]RXP, DMI[1]RXN DMI[2]TXP, DMI[2]TXN DMI[2]RXP, DMI[2]RXN DMI[3]TXP, DMI[3]TXN DMI[3]RXP, DMI[3]RXN DMI_ZCOMP DMI_IRCOMP 2.2 PCI Express* Table ...

Page 57

Link to LAN Connect Table 2-3. LAN Connect Interface Signals Name LAN_CLK LAN_RXD[2:0] LAN_TXD[2:0] LAN_RSTSYNC 2.4 EEPROM Interface Table 2-4. EEPROM Interface Signals Name Type EE_SHCLK EE_DIN EE_DOUT EE_CS 2.5 Firmware Hub Interface Table 2-5. Firmware Hub Interface Signals ...

Page 58

Signal Description 2.6 PCI Interface Table 2-6. PCI Interface Signals (Sheet Name Type AD[31:0] I/O C/BE[3:0]# I/O DEVSEL# I/O FRAME# I/O IRDY# I/O 58 Description PCI Address/Data: AD[31: multiplexed address and data bus. During the ...

Page 59

Table 2-6. PCI Interface Signals (Sheet Name Type TRDY# I/O STOP# I/O PAR I/O PERR# I/O REQ[0:3]# REQ[4]# / GPI[40] REQ[5]# / GPI[1] REQ[6]# / GPI[0] GNT[0:3]# GNT[4]# / GPO[48] O GNT[5]# / GPO[17]# GNT[6]# / GPO[16]# ...

Page 60

Signal Description Table 2-6. PCI Interface Signals (Sheet Name Type PLOCK# I/O SERR# OD I/O PME CLKRUN# (Mobile Only) / I/O GPIO[32] (Desktop Only) 2.7 Serial ATA Interface Table 2-7. Serial ATA Interface Signals (Sheet ...

Page 61

Table 2-7. Serial ATA Interface Signals (Sheet Name SATA[0]GP / GPI[26] SATA[1]GP (Desktop Only) / GPI[29] SATA[2]GP / GPI[30] SATA[3]GP (Desktop Only) / GPI[31] SATALED# 2.8 IDE Interface Table 2-8. IDE Interface Signals (Sheet ...

Page 62

Signal Description Table 2-8. IDE Interface Signals (Sheet Name Type DIOR# / (DWSTB / RDMARDY#) DIOW# / (DSTOP) IORDY / (DRSTB / WDMARDY#) 2.9 LPC Interface Table 2-9. LPC Interface Signals Name Type LAD[3:0] / I/O FWH[3:0] ...

Page 63

Interrupt Interface Table 2-10. Interrupt Signals Name Type SERIRQ I/O PIRQ[D:A PIRQ[H:E GPI[5:2] IDEIRQ ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Serial Interrupt Request: This pin implements the serial interrupt protocol. PCI ...

Page 64

Signal Description 2.11 USB Interface Table 2-11. USB Interface Signals Name USBP[0]P, USBP[0]N, USBP[1]P, USBP[1]N USBP[2]P, USBP[2]N, USBP[3]P, USBP[3]N USBP[4]P, USBP[4]N, USBP[5]P, USBP[5]N USBP[6]P, USBP[6]N, USBP[7]P, USBP[7]N OC[3:0]# OC[4]# / GPI[9] OC[5]# / GPI[10] OC[6]# / GPI[14] OC[7]# / GPI[15] ...

Page 65

Power Management Interface Table 2-12. Power Management Interface Signals (Sheet Name Type PLTRST# O THRM# I THRMTRIP# I SLP_S3# O SLP_S4# O SLP_S5# O PWROK I PWRBTN# I RI# I SYS_RESET# I RSMRST# I ® Intel ...

Page 66

Signal Description Table 2-12. Power Management Interface Signals (Sheet Name Type LAN_RST# I WAKE# I MCH_SYNC# I SUS_STAT LPCPD# SUSCLK O VRMPWRGD I BMBUSY# (Mobile Only GPI[6] (Desktop Only) STP_PCI# (Mobile Only) / ...

Page 67

Processor Interface Table 2-13. Processor Interface Signals (Sheet Name Type A20M# O CPUSLP# O FERR# I IGNNE# O INIT# O INIT3_3V# O INTR O NMI O SMI# O STPCLK# O RCIN# I ® Intel I/O Controller ...

Page 68

Signal Description Table 2-13. Processor Interface Signals (Sheet Name Type A20GATE I CPUPWRGD / OD O GPO[49] DPSLP# (Mobile Only) / TP[2] O (Desktop Only) 2.14 SMBus Interface Table 2-14. SM Bus Interface Signals Name Type SMBDATA ...

Page 69

Real Time Clock Interface Table 2-16. Real Time Clock Interface Name Type RTCX1 Special RTCX2 Special 2.17 Other Clocks Table 2-17. Other Clocks Name Type CLK14 I CLK48 I SATA_CLKP I SATA_CLKN DMI_CLKP, I DMI_CLKN 2.18 Miscellaneous Signals Table ...

Page 70

Signal Description Table 2-18. Miscellaneous Signals (Sheet Name Type TP[0] (Desktop Only) / BATLOW# (Mobile Only) TP[1] (Desktop Only) / DPRSLPVR# (Mobile Only) TP[2] (Desktop Only) / DPSLP# (Mobile Only) TP[3] TP[4] (Desktop Only) / DPRSTP# (Mobile ...

Page 71

General Purpose I/O Table 2-20. General Purpose I/O Signals Name Type GPO[49 GPO[48] O GPIO[47:42] N/A GPI[41] GPI[40] GPIO[39:35] N/A GPIO[34:33] I/O GPIO[32] I/O (Desktop Only) GPI[31] GPI[30] GPI[29] GPIO[28:27] I/O GPI[26] GPIO[25] I/O GPIO[24] I/O GPO[23] ...

Page 72

Signal Description Table 2-20. General Purpose I/O Signals Name Type GPO[18] O (Desktop Only) GPO[17] O GPO[16 GPI[15:14] 3 GPI[13] 3 GPI[12] 3 GPI[11] 3 GPI[10:9] 3 GPI[8] 3 GPI[7] 3 GPI[6] (Desktop Only) 3 GPI[5:2] 3 GPI[1:0] ...

Page 73

Power and Ground Table 2-21. Power and Ground Signals (Sheet Name 3.3 V supply for core well I/O buffers (22 pins). This power may be shut off in S3, S4 Vcc3_3 G3 states. 1.5 ...

Page 74

Signal Description Table 2-21. Power and Ground Signals (Sheet Name 1.5 V supply for core well logic (1 pins). This signal is used for the SATA PLL. This power VccSATAPLL may be shut off in S3, S4, ...

Page 75

Table 2-22. Functional Strap Definitions (Sheet Signal Usage Boot BIOS GNT[5]#/ Destination GPO[17] Selection EE_DOUT Reserved XOR Chain Entrance / ACZ_SDOUT PCI Express* Port Configu- ration bit 1 PCI Express ACZ_SYNC Port Configu- ration bit 0 TP[1] ...

Page 76

Signal Description 2.22.2 External RTC Circuitry To reduce RTC well power consumption, the ICH6 implements an internal oscillator circuit that is sensitive to step voltage changes in VccRTC. recommended to ensure correct operation of the ICH6 RTC. Figure 2-3. Example ...

Page 77

VccLAN3_3 (mobile only) must power up before VccLAN1_5 (mobile only) or after VccLAN1_5 within 0.7 V. VccLAN1_5 must power down before VccLAN3_3 or after VccLAN3_3 within 0.7 V. 2.22.3.3 3.3 V/2.5 V Power Sequencing Requirements For platforms that use the ...

Page 78

Signal Description 78 ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet ...

Page 79

Pin States 3.1 Integrated Pull-Ups and Pull-Downs Table 3-1. Integrated Pull-Up and Pull-Down Resistors Signal ACZ_BIT_CLK, AC ‘97 ACZ_RST#, AC ‘97 ACZ_SDIN[2:0], AC ‘97 ACZ_SDOUT, AC ‘97 ACZ_SYNC, AC ‘97 ACZ_BIT_CLK, Intel High Definition Audio ACZ_RST#, Intel High Definition ...

Page 80

Pin States 3. Simulation data shows that these resistor values can range from 10 kΩ kΩ. 4. Simulation data shows that these resistor values can range from 9 kΩ kΩ. 5. The pull-down resistors on ACZ_SYNC ...

Page 81

Table 3-3. Power Plane and States for Output and I/O Signals for Desktop Configurations (Sheet Signal Name PETp[1], PETn[1] PETp[2], PETn[2] PETp[3], PETn[3] PETp[4], PETn[4] AD[31:0] C/BE[3:0]# DEVSEL# FRAME# GNT[4:0]# GNT[5]# GNT[6]# IRDY#, TRDY# PAR PCIRST# PERR# ...

Page 82

Pin States Table 3-3. Power Plane and States for Output and I/O Signals for Desktop Configurations (Sheet Signal Name DA[2:0] DCS1#, DCS3# DD[15:8], DD[6:0] DD[7] DDACK# DIOR#, DIOW# SATA[0]TXP, SATA[0]TXN SATA[1]TXP, SATA[1]TXN SATA[2]TXP, SATA[2]TXN SATA[3]TXP, SATA[3]TXN SATALED# ...

Page 83

Table 3-3. Power Plane and States for Output and I/O Signals for Desktop Configurations (Sheet Signal Name A20M# CPUPWRGD CPUSLP# IGNNE# INIT# INIT3_3V# INTR NMI SMI# STPCLK# SMBCLK, SMBDATA SMLINK[1:0] LINKALERT# SPKR ACZ_RST# ACZ_SDOUT ACZ_SYNC ACZ_RST# ACZ_SDOUT ...

Page 84

Pin States Table 3-3. Power Plane and States for Output and I/O Signals for Desktop Configurations (Sheet Signal Name GPO[18] GPO[21:19] GPO[23] GPIO[24] GPIO[25] GPIO[28:27] GPIO[34:32] NOTES: 1. The states of Vcc3_3 signals are taken at the ...

Page 85

Table 3-4. Power Plane and States for Output and I/O Signals for Mobile Configurations (Sheet Power Signal Name Plane PETp[1], PETn[1] PETp[2], PETn[2] Vcc3_3 PETp[3], PETn[3] PETp[4], PETn[4] AD[31:0] Vcc3_3 C/BE[3:0]# Vcc3_3 CLKRUN# Vcc3_3 DEVSEL# Vcc3_3 FRAME# ...

Page 86

Pin States Table 3-4. Power Plane and States for Output and I/O Signals for Mobile Configurations (Sheet Power Signal Name Plane EE_CS VccLAN3_3 EE_DOUT VccLAN3_3 EE_SHCLK VccLAN3_3 LAN_RSTSYNC VccLAN3_3 LAN_TXD[2:0] VccLAN3_3 DA[2:0] Vcc3_3 DCS1#, DCS3# Vcc3_3 DD[15:8], ...

Page 87

Table 3-4. Power Plane and States for Output and I/O Signals for Mobile Configurations (Sheet Power Signal Name Plane DPRSTP# Vcc3_3 SUSCLK VccSus3_3 A20M# V_CPU_IO CPUPWRGD Vcc3_3 CPUSLP# V_CPU_IO IGNNE# V_CPU_IO INIT# V_CPU_IO INIT3_3V# Vcc3_3 INTR V_CPU_IO ...

Page 88

Pin States Table 3-4. Power Plane and States for Output and I/O Signals for Mobile Configurations (Sheet Power Signal Name Plane ACZ_RST# VccSus3_3 ACZ_SDOUT Vcc3_3 ACZ_SYNC Vcc3_3 ACZ_BIT_CLK Vcc3_3 GPO[19] Vcc3_3 GPO[21] Vcc3_3 GPO[23] Vcc3_3 GPIO[24] VccSus3_3 ...

Page 89

Power Planes for Input Signals Table 3-5 and Table 3-6 device drives the signal at various times. Valid states include: High Low Static: Will be high or low, but will not change Driven: Will be high or low, and ...

Page 90

Pin States Table 3-5. Power Plane for Input Signals for Desktop Configurations (Sheet Signal Name DMI[0]RXP, DMI[0]RXN DMI[1]RXP, DMI[1]RXN DMI[2]RXP, DMI[2]RXN DMI[3]RXP, DMI[3]RXN IDEIRQ INTRUDER# INTVRMEN IORDY LAN_CLK LAN_RST# LAN_RXD[2:0] LDRQ0# LDRQ1# MCH_SYNC# OC[7:0]# PCICLK PME# PWRBTN# ...

Page 91

Table 3-5. Power Plane for Input Signals for Desktop Configurations (Sheet Signal Name SMBALERT# SYS_RESET# THRM# THRMTRIP# TP[0] TP[3] USBRBIAS# VRMPWRGD WAKE# NOTES signal states are platform implementation specific, as some external components ...

Page 92

Pin States Table 3-6. Power Plane for Input Signals for Mobile Configurations (Sheet Signal Name Power Well GPI[13] VccSus3_3 GPI[29] GPI[31] PERp[1], PERn[1] PERp[2], PERn[2] PERp[3], PERn[3] PERp[4], PERn[4] DMI[0]RXP, DMI[0]RXN DMI[1]RXP, DMI[1]RXN DMI[2]RXP, DMI[2]RXN DMI[3]RXP, DMI[3]RXN ...

Page 93

Table 3-6. Power Plane for Input Signals for Mobile Configurations (Sheet Signal Name Power Well SATA_CLKP, SATA_CLKN SATA[0]RXP, SATA[0]RXN SATA[2]RXP, SATA[2]RXN SATARBIAS# SATA[2,0]GP SERR# SMBALERT# VccSus3_3 SYS_RESET# VccSus3_3 THRM# THRMTRIP# V_CPU_IO TP[3] VccSus3_3 USBRBIAS# VccSus3_3 VRMPWRGD WAKE# ...

Page 94

Pin States 94 ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet ...

Page 95

System Clock Domains Table 4-1 shows the ICH6 and system clock domains. assumed connection of the various system components, including the clock generator in both desktop and mobile systems. For complete details of the system clocking solution, refer to ...

Page 96

System Clock Domains Figure 4-1. Desktop Conceptual System Clock Diagram Intel ICH6 32 kHz XTAL Figure 4-2. Mobile Conceptual Clock Diagram Intel ICH6-M 32 kHz XTAL SUSCLK# (32 kHz MHz 14.31818 MHz 48.000 MHz ® 100 MHz Diff. ...

Page 97

Functional Description This chapter describes the functions and interfaces of the ICH6 Family. 5.1 PCI-to-PCI Bridge (D30:F0) The PCI-to-PCI bridge resides in PCI Device 30, Function 0 on bus #0. This portion of the ICH6 implements the buffering and ...

Page 98

Functional Description 5.1.2.1 Memory Reads and Writes The bridge bursts memory writes on PCI that are received as a single packet from DMI. The bridge will perform write combining if BPC.WCE (D30:F0:Offset 4Ch:bit 31) is set. 5.1.2.2 I/O Reads and ...

Page 99

Memory and I/O Decode to PCI The PCI bridge in the ICH6 is a subtractive decode agent, which follows the following rules when forwarding a cycle from DMI to the PCI interface: • The PCI bridge will positively decode ...

Page 100

Functional Description 5.1.4 PCIRST# The PCIRST# pin is generated under two conditions: • PLTRST# active • BCTRL.SBR (D30:F0:Offset 3Eh:bit 6) set to 1 The PCIRST# pin is in the resume well. PCIRST# should be tied to PCI bus agents, but ...

Page 101

PCI Express* Root Ports (D28:F0,F1,F2,F3) PCI Express is the next generation high performance general input/output architecture. PCI Express is a high speed, low voltage, serial pathway for two devices to communicate simultaneously by implementing dual unidirectional paths between two ...

Page 102

Functional Description 5.2.2 Power Management 5.2.2.1 S3/S4/S5 Support Software initiates the transition to S3/S4/S5 by performing an I/O write to the Power Management Control register in the ICH6. After the I/O write completion has been returned to the processor, each ...

Page 103

SMI/SCI Generation Interrupts for power management events are not supported on legacy operating systems. To support power management on non-PCI Express aware operating systems, PM events can be routed to generate SCI. To generate SCI, MPC.PMCE must be set. ...

Page 104

Functional Description When a module is removed (via the physical layer detection), the root port clears SLSTS.PDS and sets SLSTS.PDC. If SLCTL.PDE and SLCTL.HPE are both set, the root port will also generate an interrupt. 5.2.4.2 Message Generation When system ...

Page 105

SMI/SCI Generation Interrupts for Hot-Plug events are not supported on legacy operating systems. To support Hot-Plug on non-PCI Express aware operating systems, Hot-Plug events can be routed to generate SCI. To generate SCI, MPC.HPCE (D28:F0/F1/F2/F3:Offset D8h:bit 30) must be ...

Page 106

Functional Description 5.3.1 LAN Controller PCI Bus Interface As a Fast Ethernet controller, the role of the ICH6 integrated LAN controller is to access transmitted data or deposit received data. The LAN controller bus master device, initiates memory ...

Page 107

Error Handling Data Parity Errors: The LAN controller checks for data parity errors while it is the target of the transaction error was detected, the LAN controller always sets the Detected Parity Error bit in the PCI Configuration ...

Page 108

Functional Description 5.3.1.4 PCI Reset Signal The PCIRST# signal may be activated in one of the following cases: • During S3–S5 states • Due to a CF9h reset If PME is enabled (in the PCI power management registers), PCIRST# assertion ...

Page 109

When the LAN controller is in one of the low power states, it searches for a predefined pattern in the first 128 bytes of the incoming packets. The only exception is the Magic Packet, which is scanned for the entire ...

Page 110

Functional Description Figure 5-2. 64-Word EEPROM Read Instruction Waveform EE_SHCLKK EE_CS EE_DIN EE_DOUT The LAN controller performs an automatic read of seven words (0h, 1h, 2h, Ah, Bh, Ch, and Dh) of the EEPROM after the de-assertion of Reset. 5.3.3 ...

Page 111

Flow Control The LAN controller supports IEEE 802.3x frame-based flow control frames only in both full duplex and half duplex switched environments. The LAN controller flow control feature is not intended to be used in shared media environments. Flow ...

Page 112

Functional Description Table 5-3. Advanced TCO Functionality Power State Transmit Set Receive TCO Packets D0 nominal Receive TCO Packets Read ICH6 status (PM & Link state) Force TCO Mode D0 functionality plus: Dx (x>0) Read PHY registers Dx functionality plus: ...

Page 113

Read ICH6 Status (PM and Link State) The TCO controller is capable of reading the ICH6 power state and link status. Following a status change, the ICH6 asserts LINKALERT# and then the TCO can read its new power state. Set ...

Page 114

Functional Description The ASF controller provides three local configuration protocols via the host SMBus. The first one is the SMBus ARP interface that is used to identify the SMBus device and allow dynamic SMBus address assignment. The second protocol is ...

Page 115

ASF Hardware Support ASF requires additional hardware to make a complete solution. Note ASF compatible device is externally connected and properly configured, the internal ICH6 ASF controller will be disabled. The external ASF device will have access ...

Page 116

Functional Description 5.5 LPC Bridge (w/ System and Management Functions) (D31:F0) The LPC bridge function of the ICH6 resides in PCI Device 31:Function 0. In addition to the LPC bridge function, D31:F0 contains other functional units including DMA, Interrupt controllers, ...

Page 117

LPC Cycle Types The ICH6 implements all of the cycle types described in the Low Pin Count Interface Specification, Revision 1.0. Table 5-4. LPC Cycle Types Supported Cycle Type Memory Read Memory Write I/O Read I/O Write DMA Read ...

Page 118

Functional Description 5.5.1.3 Cycle Type / Direction (CYCTYPE + DIR) The ICH6 always drives bit 0 of this field to 0. Peripherals running bus master cycles must also drive bit Table 5-6 Table 5-6. Cycle Type Bit ...

Page 119

SYNC Valid values for the SYNC field are shown in Table 5-8. SYNC Bit Definition 1,2 Bits[3:0] Ready: SYNC achieved with no error. For DMA transfers, this also indicates DMA request 0000 de-assertion and no more transfers desired for ...

Page 120

Functional Description 5.5.1.9 I/O Cycles For I/O cycles targeting registers specified in the ICH6’s decode ranges, the ICH6 performs I/O cycles as defined in the Low Pin Count Interface Specification, Revision 1.1. These are 8-bit transfers. If the processor attempts ...

Page 121

Bus Master Device Mapping and START Fields Bus Masters must have a unique START field. In the case of the ICH6 that supports two LPC bus masters, it drives 0010 for the START field for grants to bus master #0 ...

Page 122

Functional Description 5.6.1 Channel Priority For priority resolution, the DMA consists of two logical channel groups: channels 0–3 and channels 4–7. Each group may be in either fixed or rotate mode, as determined by the DMA Command Register. DMA I/O ...

Page 123

Summary of DMA Transfer Sizes Table 5-9 lists each of the DMA device transfer sizes. The column labeled “Current Byte/Word Count Register” indicates that the register contents represents either the number of bytes to transfer or the number of ...

Page 124

Functional Description 5.6.5 Software Commands There are three additional special software commands that the DMA controller can execute. The three software commands are: • Clear Byte Pointer Flip-Flop • Master Clear • Clear Mask Register They do not depend on ...

Page 125

Abandoning DMA Requests DMA Requests can be de-asserted in two fashions: on error conditions by sending an LDRQ# message with the ‘ACT’ bit set normally through a SYNC field during the DMA transfer. This section describes ...

Page 126

Functional Description 5.7.4 Terminal Count Terminal count is communicated through LAD[3] on the same clock that DMA channel is communicated on LAD[2:0]. This field is the CHANNEL field. Terminal count indicates the last byte of transfer, based upon the size ...

Page 127

The peripheral must not assume that the next START indication from the ICH6 is another grant to the peripheral if it had indicated a SYNC value of 1001b single mode DMA device, the 8237 will re-arbitrate after every ...

Page 128

Functional Description 5.8 8254 Timers (D31:F0) The ICH6 contains three counters that have fixed uses. All registers and functions associated with the 8254 timers are in the core well. The 8254 unit is clocked by a 14.31818 MHz clock. Counter ...

Page 129

If a counter is programmed to read/write two-byte counts, the following precaution applies: A program must not transfer control between writing the first and second byte to another routine which also writes into that same counter. Otherwise, the counter will ...

Page 130

Functional Description 5.8.2.1 Simple Read The first method is to perform a simple read operation. The counter is selected through port 40h (counter 0), 41h (counter 1), or 42h (counter 2). Note: Performing a direct read from the counter does ...

Page 131

Interrupt Controllers (PIC) (D31:F0) The ICH6 incorporates the functionality of two 8259 interrupt controllers that provide system interrupts for the ISA compatible interrupts. These interrupts are: system timer, keyboard controller, serial ports, parallel ports, floppy disk, IDE, mouse, ...

Page 132

Functional Description 5.9.1 Interrupt Handling 5.9.1.1 Generating Interrupts The PIC interrupt sequence involves three bits, from the IRR, ISR, and IMR, for each interrupt level. These bits are used to determine the interrupt vector returned, and status of any other ...

Page 133

Hardware/Software Interrupt Sequence 1. One or more of the Interrupt Request lines (IRQ) are raised high in edge mode, or seen high in level mode, setting the corresponding IRR bit. 2. The PIC sends INTR active to the processor ...

Page 134

Functional Description 5.9.2.2 ICW2 The second write in the sequence (ICW2) is programmed to provide bits [7:3] of the interrupt vector that will be released during an interrupt acknowledge. A different base is selected for each interrupt controller. 5.9.2.3 ICW3 ...

Page 135

Special Fully-Nested Mode This mode is used in the case of a system where cascading is used, and the priority has to be conserved within each slave. In this case, the special fully-nested mode is programmed to the master ...

Page 136

Functional Description 5.9.4.6 Cascade Mode The PIC in the ICH6 has one master 8259 and one slave 8259 cascaded onto the master through IRQ2. This configuration can handle separate priority levels. The master controls the slaves through ...

Page 137

Masking Interrupts 5.9.5.1 Masking on an Individual Interrupt Request Each interrupt request can be masked individually by the Interrupt Mask Register (IMR). This register is programmed through OCW1. Each bit in the IMR masks one interrupt channel. Masking IRQ2 ...

Page 138

Functional Description 5.10 Advanced Programmable Interrupt Controller (APIC) (D31:F0) In addition to the standard ISA-compatible PIC described in the previous chapter, the ICH6 incorporates the APIC. While the standard interrupt controller is intended for use in a uni-processor system, APIC ...

Page 139

Table 5-15. APIC Interrupt Mapping (Sheet Via IRQ # SERIRQ 16 PIRQA# 17 PIRQB# 18 PIRQC# 19 PIRQD# 20 N/A 21 N/A 22 N/A 23 N/A NOTES: 1. IDEIRQ can only be driven directly from the pin ...

Page 140

Functional Description 5.10.4.1 Edge-Triggered Operation In this case, the “Assert Message” is sent when there is an inactive-to-active edge on the interrupt. 5.10.4.2 Level-Triggered Operation In this case, the “Assert Message” is sent when there is an inactive-to-active edge on ...

Page 141

Table 5-17. Interrupt Message Data Format Bit 31:16 Will always be 0000h. Trigger Mode Level Edge. Same as the corresponding bit in the I/O Redirection Table 15 for that interrupt. 14 Delivery Status Assert, ...

Page 142

Functional Description 5.11.1 Start Frame The serial IRQ protocol has two modes of operation which affect the start frame. These two modes are: Continuous, where the ICH6 is solely responsible for generating the start frame; and Quiet, where a serial ...

Page 143

Specific Interrupts Not Supported via SERIRQ There are three interrupts seen through the serial stream that are not supported by the ICH6. These interrupts are generated internally, and are not sharable with other devices within the system. These interrupts ...

Page 144

Functional Description 5.12 Real Time Clock (D31:F0) The Real Time Clock (RTC) module provides a battery backed-up date and time keeping device with two banks of static RAM with 128 bytes each, although the first bank has 114 bytes for ...

Page 145

Interrupts The real-time clock interrupt is internally routed within the ICH6 both to the I/O APIC and the 8259 mapped to interrupt vector 8. This interrupt does not leave the ICH6, nor is it shared with any ...

Page 146

Functional Description Table 5-20. Configuration Bits Reset by RTCRST# Assertion Bit Name Alarm Interrupt Enable (AIE) Alarm Flag (AF) SWSMI_RATE_SEL SLP_S4# Minimum Assertion Width SLP_S4# Assertion Stretch Enable RTC Power Status (RTC_PWR_STS) Power Failure (PWR_FLR) AFTERG3_EN Power Button Override Status ...

Page 147

Using a GPI to Clear CMOS A jumper on a GPI can also be used to clear CMOS values. BIOS would detect the setting of this GPI on system boot-up, and manually clear the CMOS array. Note: The GPI strap ...

Page 148

Functional Description Table 5-21. INIT# Going Active Cause of INIT# Going Active Shutdown special cycle from processor. PORT92 write, where INIT_NOW (bit 0) transitions from PORTCF9 write, where SYS_RST (bit 1) was a 0 and ...

Page 149

NMI (Non-Maskable Interrupt) Non-Maskable Interrupts (NMIs) can be generated by several sources, as described in Table 5-22. NMI Sources Cause of NMI SERR# goes active (either internally, externally via SERR# signal, or via message from (G)MCH) IOCHK# goes active ...

Page 150

Functional Description 5.13.2.2 Power Management For multiple-processor (or multiple-core) configurations in which more than one Stop Grant cycle may be generated, the (G)MCH is expected to count Stop Grant cycles and only pass the last one through to the ICH6. ...

Page 151

Intel ICH6 and System Power States Table 5-24 shows the power states defined for ICH6-based platforms. The state names generally match the corresponding ACPI states. Table 5-24. General Power States for Systems Using Intel State/ Substates Full On: ...

Page 152

Functional Description Table 5-25. State Transition Rules for Intel Present State • Processor halt instruction • Level 2 Read • Level 3 Read (Mobile Only) • Level 4 Read (Mobile Only) G0/S0/C0 • SLP_EN bit set • Power Button Override ...

Page 153

System Power Planes The system has several independent power planes, as described in particular power plane is shut off, it should level. s Table 5-26. System Power Plane Controlled Plane SLP_S3# Processor SLP_S3# (S3 ...

Page 154

Functional Description Table 5-27 shows which events can cause an SMI# and SCI. Note that some events can be programmed to cause either an SMI# or SCI. The usage of the event for SCI (instead of SMI#) is typically associated ...

Page 155

Table 5-27. Causes of SMI# and SCI (Sheet 1-5 Cause BIOS_RLS written to GBL_RLS written to Write to B2h register Periodic timer expires 64 ms timer expires Enhanced USB Legacy Support Event Enhanced USB Intel Specific Event ...

Page 156

Functional Description 5.14.5 Dynamic Processor Clock Control The ICH6 has extensive control for dynamically starting and stopping system clocks. The clock control is used for transitions among the various S0/Cx states, and processor throttling. Each dynamic clock control method is ...

Page 157

Table 5-28. Break Events (Mobile Only) (Sheet Event Any internal event that cause INIT active Any bus master request (internal, external or DMA, or BMBUSY#) goes active and BM_RLD=1 (D31:F0:Offset PMBASE+04h: bit 1) Processor Pending ...

Page 158

Functional Description To take advantage of the Deferred C3/C4 mode, the BM_STS_ZERO_EN bit must be set. This will cause the BM_STS bit to read as 0 even if some bus master activity is present. If this is not done, then ...

Page 159

Behavioral Description • When there is a lack of activity (as defined above) for 29 PCI clocks, the ICH6 de-asserts (drive high) CLKRUN# for 1 clock and then tri-states the signal. 5.14.6.2 Conditions for Maintaining the PCI Clock PCI masters ...

Page 160

Functional Description 5.14.7 Sleep States 5.14.7.1 Sleep State Overview The ICH6 directly supports different sleep states (S1–S5), which are entered by setting the SLP_EN bit, or due to a Power Button press. The entry to the Sleep states are based ...

Page 161

Table 5-30. Causes of Wake Events 1,2 Cause RTC Alarm Power Button GPI[0:15] Classic USB LAN RI# AC ‘97 / Intel High Definition Audio Primary PME# Secondary PME# PCI_EXP_WAKE# PCI_EXP PME Message SMBALERT# SMBus Slave Message SMBus Host Notify message ...

Page 162

Functional Description 5.14.7.4 PCI Express* WAKE# Signal and PME Event Message PCI Express ports can wake the platform from any sleep state (S1, S3, S4, or S5) using the WAKE# pin. WAKE# is treated as a wake event, but does ...

Page 163

Thermal Management The ICH6 has mechanisms to assist with managing thermal problems in the system. 5.14.8.1 THRM# Signal The THRM# signal is used as a status input for a thermal sensor. Based on the THRM# signal going active, the ...

Page 164

Functional Description 5.14.9 Event Input Signals and Their Usage The ICH6 has various input signals that trigger specific events. This section describes those signals and how they should be used. 5.14.9.1 PWRBTN# (Power Button) The ICH6 PWRBTN# signal operates as ...

Page 165

Power Button must be pressed for another seconds to create the Override condition to S5. Sleep Button The Advanced Configuration and Power Interface, Version 2.0b defines an optional Sleep button. It differs from ...

Page 166

Functional Description 5.14.9.5 THRMTRIP# Signal If THRMTRIP# goes active, the processor is indicating an overheat condition, and the ICH6 immediately transitions state. However, since the processor has overheated, it does not respond to the ICH6’s STPCLK# pin ...

Page 167

ALT Access Mode Before entering a low power state, several registers from powered down parts may need to be saved. In the majority of cases, this is not an issue, as registers have read and write paths. However, several ...

Page 168

Functional Description 5.14.10.1 Write Only Registers with Read Paths in ALT Access Mode The registers described in field in the table indicates which register will be returned per access to that port. Table 5-35. Write Only Registers with Read Paths ...

Page 169

Table 5-35. Write Only Registers with Read Paths in ALT Access Mode (Sheet Restore Data I Access Addr Rds 1 PIC ICW2 of Master controller 2 PIC ICW3 of Master controller 3 PIC ICW4 of ...

Page 170

Functional Description 5.14.10.3 Read Only Registers with Write Paths in ALT Access Mode The registers described in restores these values after returning from a powered down state. These registers must be handled special by software. When in normal mode, writing ...

Page 171

SLP_S4# and Suspend-To-RAM Sequencing The system memory suspend voltage regulator is controlled by the Glue logic. The SLP_S4# signal should be used to remove power to system memory rather than the SLP_S5# signal. The SLP_S4# logic in the ICH6 ...

Page 172

Functional Description 5.14.11.7 Controlling Leakage and Power Consumption During Low-Power States To control leakage in the system, various signals tri-state or go low during some low-power states. General principles: • All signals going to powered down planes (either internally or ...

Page 173

Clock Control Signals from Intel Synthesizer (Mobile Only) The clock generator is assumed to have direct connect from the following ICH6 signals: • STP_CPU# • STP_PCI# • SLP_S3# 5.14.13 Legacy Power Management Theory of Operation Instead of relying on ...

Page 174

Functional Description 5.15 System Management (D31:F0) The ICH6 provides various functions to make a system easier to manage and to lower the Total Cost of Ownership (TCO) of the system. In addition, ICH6 provides integrated ASF Management support. Features and ...

Page 175

If the INTRUDER# signal goes inactive some point after the INTRD_DET bit is written then the INTRD_DET signal will when INTRUDER# input signal goes inactive. Note that this is slightly different than a ...

Page 176

Functional Description The following rules/steps apply if the system state and the policy is for the ICH6 to reboot the system after a hardware lockup detecting the lockup, the SECOND_TO_STS bit is set. The ...

Page 177

After step 4 (power button override), if the user presses the power button again, the system should wake state and the processor should start executing the BIOS step 5 (power button press) is successful ...

Page 178

Functional Description and would prevent an operating system’s device driver from sending or receiving some messages system that has locked up and can not be restarted with power button press is assumed to have broken hardware (bad power ...

Page 179

IDE Controller (D31:F1) The ICH6 IDE controller features one sets of interface signals that can be enabled, tri-stated or driven low. The IDE interfaces of the ICH6 can support several types of data transfers: • Programmed I/O (PIO): Processor ...

Page 180

Functional Description If IORDY is asserted when the initial sample point is reached, no wait-states are added to the command strobe assertion length. If IORDY is negated when the initial sample point is reached, additional wait-states are added. Since the ...

Page 181

Bus Master Function The ICH6 can act as a PCI Bus master on behalf of an IDE device. One PCI Bus master channel is provided for the IDE connector. By performing the IDE data transfer as a PCI Bus ...

Page 182

Functional Description 5.16.2.2 Bus Master IDE Timings The timing modes used for Bus Master IDE transfers are identical to those for PIO transfers. The DMA Timing Enable Only bits in IDE Timing register can be used to program fast timing ...

Page 183

The last PRD in a table has the End of List (EOL) bit set. The PCI bus master data transfers terminate when the physical region described by the last PRD in the table has been completely transferred. The active bit ...

Page 184

Functional Description 5.16.3 Ultra ATA/100/66/33 Protocol The ICH6 supports Ultra ATA/100/66/33 bus mastering protocol, providing support for a variety of transfer speeds with IDE devices. Ultra ATA/33 provides transfers MB/s, Ultra ATA/66 provides transfers ...

Page 185

Ultra ATA/33/66/100 Timing The timings for Ultra ATA/33/66/100 modes are programmed via the Synchronous DMA Timing register and the IDE Configuration register. Different timings can be programmed for each drive in the system. The Base Clock frequency for each ...

Page 186

Functional Description 5.17 SATA Host Controller (D31:F2) The SATA function in the ICH6 has dual modes of operation to support different operating system conditions. In the case of Native IDE enabled operating systems, the ICH6 has separate PCI functions for ...

Page 187

LBA Operation The SATA host controller supports 48-bit LBA through the host-to-device register FIS when accesses are performed via writes to the task file. The SATA host controller will ensure that the correct data is put into the ...

Page 188

Functional Description • Provides a text mode user interface that allows the user to manage the RAID configuration on the system in a pre-operating system environment. Its feature set is kept simple to keep size to a minimum, but allows ...

Page 189

Figure 5-8. SATA Power States PHY = Ready 5.17.4.2 Power State Transitions 5.17.4.2.1 Partial and Slumber State Entry/Exit The partial and slumber states save interface power when the interface is idle. It would be most analogous to PCI CLKRUN# (in ...

Page 190

Functional Description When the controller is put into D3 assumed that software has properly shut down the device and disabled the ports. Therefore, there is no need to sustain any values on the port wires. The interface will ...

Page 191

High Precision Event Timers This function provides a set of timers that can be used by the operating system. The timers are defined such that in the future, the operating system may be able to assign specific timers to ...

Page 192

Functional Description 5.18.3 Periodic vs. Non-Periodic Modes Non-Periodic Mode Timer 0 is configurable to 32 (default) or 64-bit mode, whereas Timers 1 and 2 only support 32-bit mode (See Section All three timers support non-periodic mode. Consult section 2.3.9.2.1 of ...

Page 193

Interrupt Levels Interrupts directed to the internal 8259s are active high. See the polarity programming of the I/O APIC for detecting internal interrupts. If the interrupts are mapped to the I/O APIC and set for level-triggered mode, they can ...

Page 194

Functional Description 5.19 USB UHCI Host Controllers (D29:F0, F1, F2, and F3) The ICH6 contains four USB 2.0 full/low-speed host controllers that support the standard Universal Host Controller Interface (UHCI), Revision 1.1. Each UHCI Host Controller (UHC) includes a root ...

Page 195

Packet Field Formats All packets have distinct start and end of packet delimiters. Full details are given in the Universal Serial Bus Revision 2.0 Specification in section 8.3.1. 5.19.4.4 Address Fields Function endpoints are addressed using the function address ...

Page 196

Functional Description 5.19.6.1 Transaction-Based Interrupts These interrupts are not signaled until after the status for the last complete transaction in the frame has been written back to host memory. This guarantees that software can safely process through (Frame List Current ...

Page 197

Serial Bus Babble When a device transmits on the USB for a time greater than its assigned Max Length said to be babbling. Since isochrony can be destroyed by a babbling device, this error results in the Active ...

Page 198

Functional Description 5.19.6.2 Non-Transaction Based Interrupts If an ICH6 process error or system error occur, the ICH6 halts and immediately issues a hardware interrupt to the system. Resume Received This event indicates that the ICH6 received a RESUME signal from ...

Page 199

USB Legacy Keyboard Operation When a USB keyboard is plugged into the system, and a standard keyboard is not, the system may not boot, and MS-DOS legacy software will not run, because the keyboard will not be identified. The ...

Page 200

Functional Description Table 5-44. USB Legacy Keyboard State Transitions Current State Action IDLE 64h / Write IDLE 64h / Write IDLE 64h / Read IDLE 60h / Write IDLE 60h / Read GateState1 60h / Write GateState1 64h / Write ...

Related keywords