FDC37C665GT Standard Microsystems (SMSC), FDC37C665GT Datasheet - Page 110

• Manufacturer Part Number: FDC37C665GT
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C665GT

• Lead Free Status / RoHS Status: Not Compliant

are
mode using program control of the control
signals.
Interrupts
The interrupts are enabled by serviceIntr in the
ecr register.
serviceIntr = 1 Disables the DMA and all of the
serviceIntr = 0Enables the selected interrupt
The interrupt generated is ISA friendly in that it
must pulse the interrupt line low, allowing for
interrupt sharing.
following the interrupt event, the interrupt line is
tri-stated so that other interrupts may assert.
An interrupt is generated when:
1. For DMA transfers: When serviceIntr is 0,
2. For Programmed I/O:
dmaEn is 1 and the DMA TC is received.
a.
always possible with standard or PS/2
When serviceIntr is 0, dmaEn is 0,
direction
writeIntrThreshold or more free bytes in
the FIFO.
generated when serviceIntr is cleared
to
writeIntrThreshold or more free bytes in
the FIFO.
0
service interrupts.
condition.
condition is valid, then the
interrupt
immediately when this bit is
changed from a 1 to a 0. This
can occur during Programmed
I/O if the number of bytes
removed or added from/to the
FIFO does not cross the
threshold.
is
whenever
After a brief pulse low
Also, an interrupt is
0
and
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110
3. When nErrIntrEn is 0 and nFault transitions
4. When ackIntEn is 1 and the nAck signal
FIFO Operation
The
configuration registers. All data transfers to or
from the parallel port can proceed in DMA or
Programmed I/O (non-DMA) mode as indicated
by the selected mode.
selecting the Parallel Port FIFO mode or ECP
Parallel Port Mode. (FIFO test mode will be
addressed separately.) After a reset, the FIFO
is disabled. Each data byte is transferred by a
Programmed I/O cycle or PDRQ depending on
the selection of DMA or Programmed I/O mode.
The following paragraphs detail the operation of
the FIFO flow control.
<threshold> ranges from 1 to 16.
parameter FIFOTHR, which the user programs,
is one less and ranges from 0 to 15.
A low threshold value (i.e. 2) results in longer
periods of time between service requests, but
requires faster servicing of the request for both
read and write cases. The host must be very
responsive to the service request. This is the
desired case for use with a "fast" system.
b.
from high to low or when nErrIntrEn is set
from 1 to 0 and nFault is asserted.
transitions from a low to a high.
FIFO
(1)
threshold
When serviceIntr is 0, dmaEn
is 0, direction is 1 and there
are readIntrThreshold or more
bytes in the FIFO.
interrupt is generated when
serviceIntr is cleared to 0
whenever
readIntrThreshold
bytes in the FIFO.
is
The FIFO is used by
In these descriptions,
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