FDC37C665GT Standard Microsystems (SMSC), FDC37C665GT Datasheet - Page 138

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FDC37C665GT

Manufacturer Part Number
FDC37C665GT
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet

Specifications of FDC37C665GT

Lead Free Status / RoHS Status
Not Compliant

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(AT Mode timing only)
*X specifies one MCLK period and Y specifies one WCLK period.
MCLK = Controller Clock to FDC (See Table 6).
WCLK = 2 x Data Rate (See Table 6).
t1
t2
t3
t4
t5
t6
t7
t8
t9
nDS0-3,
MTR0-3
nWDATA
nRDATA
nDS0-3
nINDEX
nSTEP
nIOW
nDIR
nDIR Set Up to nSTEP Low
nSTEP Active Time Low
nDIR Hold Time After nSTEP
nSTEP Cycle Time
nDS0-3 Hold Time from nSTEP Low
nINDEX Pulse Width
nRDATA Active Time Low
nWDATA Write Data Width Low
nDS0-3, MTR0-3 from End of nIOW
Parameter
t9
FIGURE 9 - DISK DRIVE TIMING
t1
t6
t7
t8
138
t2
min
t4
typ
132
t3
t5
24
96
20
40
25
.5
4
2
max
t9
units
ns
X*
X*
X*
X*
X*
X*
ns
Y*

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