PSD834F2-15J STMicroelectronics, PSD834F2-15J Datasheet - Page 53
PSD834F2-15J
Manufacturer Part Number
PSD834F2-15J
Description
Manufacturer
STMicroelectronics
Datasheet
1.PSD834F2-15J.pdf
(95 pages)
Specifications of PSD834F2-15J
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Package Type
PLCC
Mounting
Surface Mount
Pin Count
52
Lead Free Status / RoHS Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PSD834F2-15J
Manufacturer:
INTEL
Quantity:
860
Port C – Functionality and Structure
Port C can be configured to perform one or more
of the following functions (see Figure 25):
■
■
■
■
■
Figure 25. Port C Structure
MCU I/O Mode
CPLD Output – McellBC7-McellBC0 outputs
can be connected to Port B or Port C.
CPLD Input – via the Input Macrocells (IMC)
Address In – Additional high address inputs
using the Input Macrocells (IMC).
In-System Programming (ISP) – JTAG port can
be enabled for programming/erase of the PSD
WR
MCELLBC [ 7:0 ]
WR
ENABLE PRODUCT TERM ( .OE )
CPLD -INPUT
READ MUX
DATA OUT
DIR REG.
D
D
REG.
D
B
P
Q
Q
DATA IN
SPECIAL FUNCTION
DATA OUT
■
Port C does not support Address Out mode, and
therefore no Control Register is required.
Pin PC7 may be configured as the DBE input in
certain MCU bus interfaces.
device. (See the section entitled
“PROGRAMMING IN-CIRCUIT USING THE
JTAG SERIAL INTERFACE”, on page 63, for
more information on JTAG programming.)
Open Drain – Port C pins can be configured in
Open Drain Mode
1
SPECIAL FUNCTION
OUTPUT
SELECT
OUTPUT
MUX
ENABLE OUT
MACROCELL
1
INPUT
CONFIGURATION
PORT C PIN
PSD834F2V
BIT
AI02888B
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